Lines Matching refs:MF
59 static void getVGPRSpillLaneOrTempRegister(MachineFunction &MF, in getVGPRSpillLaneOrTempRegister() argument
64 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in getVGPRSpillLaneOrTempRegister()
65 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in getVGPRSpillLaneOrTempRegister()
67 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister()
74 if (MFI->haveFreeLanesForSGPRSpill(MF, 1)) { in getVGPRSpillLaneOrTempRegister()
78 if (!MFI->allocateSGPRSpillToVGPR(MF, NewFI)) in getVGPRSpillLaneOrTempRegister()
92 MF.getRegInfo(), LiveRegs, AMDGPU::SReg_32_XM0_XEXECRegClass, true); in getVGPRSpillLaneOrTempRegister()
98 if (TRI->spillSGPRToVGPR() && MFI->allocateSGPRSpillToVGPR(MF, NewFI)) { in getVGPRSpillLaneOrTempRegister()
109 MF.getFrameInfo().RemoveStackObject(NewFI); in getVGPRSpillLaneOrTempRegister()
126 LivePhysRegs &LiveRegs, MachineFunction &MF, in buildPrologSpill() argument
133 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in buildPrologSpill()
134 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI); in buildPrologSpill()
135 MachineMemOperand *MMO = MF.getMachineMemOperand( in buildPrologSpill()
148 LivePhysRegs &LiveRegs, MachineFunction &MF, in buildEpilogRestore() argument
155 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in buildEpilogRestore()
156 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI); in buildEpilogRestore()
157 MachineMemOperand *MMO = MF.getMachineMemOperand( in buildEpilogRestore()
168 MachineFunction *MF = MBB.getParent(); in buildGitPtr() local
169 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); in buildGitPtr()
183 Register GitPtrLo = MFI->getGITPtrLoReg(*MF); in buildGitPtr()
184 MF->getRegInfo().addLiveIn(GitPtrLo); in buildGitPtr()
192 MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, in emitEntryFunctionFlatScratchInit() argument
194 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
197 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in emitEntryFunctionFlatScratchInit()
219 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionFlatScratchInit()
221 ArrayRef<MCPhysReg> AllSGPR64s = TRI->getAllSGPR64(MF); in emitEntryFunctionFlatScratchInit()
225 Register GITPtrLoReg = MFI->getGITPtrLoReg(MF); in emitEntryFunctionFlatScratchInit()
244 auto *MMO = MF.getMachineMemOperand( in emitEntryFunctionFlatScratchInit()
250 MF.getFunction().getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0; in emitEntryFunctionFlatScratchInit()
251 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
269 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionFlatScratchInit()
340 MachineFunction &MF) const { in getEntryFunctionReservedScratchRsrcReg()
342 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getEntryFunctionReservedScratchRsrcReg()
345 MachineRegisterInfo &MRI = MF.getRegInfo(); in getEntryFunctionReservedScratchRsrcReg()
346 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in getEntryFunctionReservedScratchRsrcReg()
353 allStackObjectsAreDead(MF.getFrameInfo()))) in getEntryFunctionReservedScratchRsrcReg()
357 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF)) in getEntryFunctionReservedScratchRsrcReg()
370 ArrayRef<MCPhysReg> AllSGPR128s = TRI->getAllSGPR128(MF); in getEntryFunctionReservedScratchRsrcReg()
375 Register GITPtrLoReg = MFI->getGITPtrLoReg(MF); in getEntryFunctionReservedScratchRsrcReg()
395 void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, in emitEntryFunctionPrologue() argument
397 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); in emitEntryFunctionPrologue()
410 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in emitEntryFunctionPrologue()
411 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionPrologue()
414 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionPrologue()
415 const Function &F = MF.getFunction(); in emitEntryFunctionPrologue()
416 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in emitEntryFunctionPrologue()
434 ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF); in emitEntryFunctionPrologue()
438 for (MachineBasicBlock &OtherBB : MF) { in emitEntryFunctionPrologue()
471 ArrayRef<MCPhysReg> AllSGPRs = TRI->getAllSGPR32(MF); in emitEntryFunctionPrologue()
475 Register GITPtrLoReg = MFI->getGITPtrLoReg(MF); in emitEntryFunctionPrologue()
490 if (requiresStackPointerReference(MF)) { in emitEntryFunctionPrologue()
497 if (hasFP(MF)) { in emitEntryFunctionPrologue()
515 emitEntryFunctionFlatScratchInit(MF, MBB, I, DL, ScratchWaveOffsetReg); in emitEntryFunctionPrologue()
519 emitEntryFunctionScratchRsrcRegSetup(MF, MBB, I, DL, in emitEntryFunctionPrologue()
527 MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, in emitEntryFunctionScratchRsrcRegSetup() argument
531 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionScratchRsrcRegSetup()
534 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in emitEntryFunctionScratchRsrcRegSetup()
535 const Function &Fn = MF.getFunction(); in emitEntryFunctionScratchRsrcRegSetup()
549 auto MMO = MF.getMachineMemOperand(PtrInfo, in emitEntryFunctionScratchRsrcRegSetup()
555 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionScratchRsrcRegSetup()
590 if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { in emitEntryFunctionScratchRsrcRegSetup()
600 auto MMO = MF.getMachineMemOperand( in emitEntryFunctionScratchRsrcRegSetup()
612 MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR()); in emitEntryFunctionScratchRsrcRegSetup()
684 MachineFunction &MF, MachineBasicBlock &MBB, in initLiveRegs() argument
700 MachineFunction &MF, in buildScratchExecCopy() argument
705 MachineRegisterInfo &MRI = MF.getRegInfo(); in buildScratchExecCopy()
706 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in buildScratchExecCopy()
709 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in buildScratchExecCopy()
712 initLiveRegs(LiveRegs, TRI, FuncInfo, MF, MBB, MBBI, IsProlog); in buildScratchExecCopy()
730 static bool spilledToMemory(const MachineFunction &MF, int SaveIndex) { in spilledToMemory() argument
731 const MachineFrameInfo &MFI = MF.getFrameInfo(); in spilledToMemory()
735 void SIFrameLowering::emitPrologue(MachineFunction &MF, in emitPrologue() argument
737 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in emitPrologue()
739 emitEntryFunctionPrologue(MF, MBB); in emitPrologue()
743 const MachineFrameInfo &MFI = MF.getFrameInfo(); in emitPrologue()
744 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue()
745 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitPrologue()
752 TRI.hasBasePointer(MF) ? TRI.getBaseRegister() : Register(); in emitPrologue()
776 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, in emitPrologue()
779 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitPrologue()
792 buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, /*IsProlog*/ true); in emitPrologue()
794 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI); in emitPrologue()
806 if (FPSaveIndex && spilledToMemory(MF, *FPSaveIndex)) { in emitPrologue()
810 initLiveRegs(LiveRegs, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ true); in emitPrologue()
820 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
824 if (BPSaveIndex && spilledToMemory(MF, *BPSaveIndex)) { in emitPrologue()
828 initLiveRegs(LiveRegs, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ true); in emitPrologue()
838 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
843 if (FPSaveIndex && !spilledToMemory(MF, *FPSaveIndex)) { in emitPrologue()
860 if (BPSaveIndex && !spilledToMemory(MF, *BPSaveIndex)) { in emitPrologue()
902 for (MachineBasicBlock &MBB : MF) { in emitPrologue()
914 if (TRI.hasStackRealignment(MF)) { in emitPrologue()
935 } else if ((HasFP = hasFP(MF))) { in emitPrologue()
945 if ((HasBP = TRI.hasBasePointer(MF))) { in emitPrologue()
975 void SIFrameLowering::emitEpilogue(MachineFunction &MF, in emitEpilogue() argument
977 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in emitEpilogue()
981 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEpilogue()
983 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEpilogue()
989 const MachineFrameInfo &MFI = MF.getFrameInfo(); in emitEpilogue()
997 TRI.hasBasePointer(MF) ? TRI.getBaseRegister() : Register(); in emitEpilogue()
1002 if (RoundedSize != 0 && hasFP(MF)) { in emitEpilogue()
1024 if (spilledToMemory(MF, FramePtrFI)) { in emitEpilogue()
1025 initLiveRegs(LiveRegs, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ false); in emitEpilogue()
1031 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitEpilogue()
1050 if (spilledToMemory(MF, BasePtrFI)) { in emitEpilogue()
1051 initLiveRegs(LiveRegs, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ false); in emitEpilogue()
1057 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitEpilogue()
1081 buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, /*IsProlog*/ false); in emitEpilogue()
1083 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitEpilogue()
1095 buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, /*IsProlog*/ false); in emitEpilogue()
1097 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI); in emitEpilogue()
1110 static bool allSGPRSpillsAreDead(const MachineFunction &MF) { in allSGPRSpillsAreDead() argument
1111 const MachineFrameInfo &MFI = MF.getFrameInfo(); in allSGPRSpillsAreDead()
1112 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in allSGPRSpillsAreDead()
1127 StackOffset SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, in getFrameIndexReference() argument
1130 const SIRegisterInfo *RI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in getFrameIndexReference()
1132 FrameReg = RI->getFrameRegister(MF); in getFrameIndexReference()
1133 return StackOffset::getFixed(MF.getFrameInfo().getObjectOffset(FI)); in getFrameIndexReference()
1137 MachineFunction &MF, in processFunctionBeforeFrameFinalized() argument
1139 MachineFrameInfo &MFI = MF.getFrameInfo(); in processFunctionBeforeFrameFinalized()
1141 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in processFunctionBeforeFrameFinalized()
1144 MachineRegisterInfo &MRI = MF.getRegInfo(); in processFunctionBeforeFrameFinalized()
1145 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in processFunctionBeforeFrameFinalized()
1156 for (MachineBasicBlock &MBB : MF) { in processFunctionBeforeFrameFinalized()
1173 if (FuncInfo->allocateVGPRSpillToAGPR(MF, FI, in processFunctionBeforeFrameFinalized()
1185 for (MachineBasicBlock &MBB : MF) { in processFunctionBeforeFrameFinalized()
1210 assert(allSGPRSpillsAreDead(MF) && in processFunctionBeforeFrameFinalized()
1225 void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, in determineCalleeSaves() argument
1228 TargetFrameLowering::determineCalleeSaves(MF, SavedVGPRs, RS); in determineCalleeSaves()
1229 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in determineCalleeSaves()
1233 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in determineCalleeSaves()
1234 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determineCalleeSaves()
1266 if (WillHaveFP || hasFP(MF)) { in determineCalleeSaves()
1269 getVGPRSpillLaneOrTempRegister(MF, LiveRegs, MFI->SGPRForFPSaveRestoreCopy, in determineCalleeSaves()
1273 if (TRI->hasBasePointer(MF)) { in determineCalleeSaves()
1279 getVGPRSpillLaneOrTempRegister(MF, LiveRegs, MFI->SGPRForBPSaveRestoreCopy, in determineCalleeSaves()
1284 void SIFrameLowering::determineCalleeSavesSGPR(MachineFunction &MF, in determineCalleeSavesSGPR() argument
1287 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); in determineCalleeSavesSGPR()
1288 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in determineCalleeSavesSGPR()
1292 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determineCalleeSavesSGPR()
1306 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in determineCalleeSavesSGPR()
1310 if (WillHaveFP || hasFP(MF)) in determineCalleeSavesSGPR()
1315 MachineFunction &MF, const TargetRegisterInfo *TRI, in assignCalleeSavedSpillSlots() argument
1320 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in assignCalleeSavedSpillSlots()
1325 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in assignCalleeSavedSpillSlots()
1353 MachineFunction &MF, in eliminateCallFramePseudoInstr() argument
1360 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in eliminateCallFramePseudoInstr()
1367 if (!hasReservedCallFrame(MF)) { in eliminateCallFramePseudoInstr()
1370 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in eliminateCallFramePseudoInstr()
1400 bool SIFrameLowering::hasFP(const MachineFunction &MF) const { in hasFP()
1401 const MachineFrameInfo &MFI = MF.getFrameInfo(); in hasFP()
1406 !MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction()) { in hasFP()
1416 MF.getSubtarget<GCNSubtarget>().getRegisterInfo()->hasStackRealignment( in hasFP()
1417 MF) || in hasFP()
1418 MF.getTarget().Options.DisableFramePointerElim(MF); in hasFP()
1427 const MachineFunction &MF) const { in requiresStackPointerReference()
1429 assert(MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction() && in requiresStackPointerReference()
1432 const MachineFrameInfo &MFI = MF.getFrameInfo(); in requiresStackPointerReference()