501   MachineInstr *Def = MRI.getVRegDef(UseReg);  in getRegSeqInit()  local
502   if (!Def || !Def->isRegSequence())  in getRegSeqInit()
505   for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) {  in getRegSeqInit()
506     MachineOperand *Sub = &Def->getOperand(I);  in getRegSeqInit()
524     Defs.emplace_back(Sub, Def->getOperand(I + 1).getImm());  in getRegSeqInit()
566   MachineInstr *Def = MRI.getVRegDef(UseReg);  in tryToFoldACImm()  local
568   if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) {  in tryToFoldACImm()
569     MachineOperand &DefOp = Def->getOperand(1);  in tryToFoldACImm()
770           MachineOperand *Def = Defs[I].first;  in foldOperand()  local
772           if (Def->isImm() &&  in foldOperand()
773               TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {  in foldOperand()
774             int64_t Imm = Def->getImm();  in foldOperand()
780           } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {  in foldOperand()
781             auto Src = getRegSubRegPair(*Def);  in foldOperand()
782             Def->setIsKill(false);  in foldOperand()
789               B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,  in foldOperand()
793             assert(Def->isReg());  in foldOperand()
794             Def->setIsKill(false);  in foldOperand()
795             auto Src = getRegSubRegPair(*Def);  in foldOperand()
804               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);  in foldOperand()
815               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);  in foldOperand()
1036     MachineInstr *Def = MRI.getVRegDef(Op.getReg());  in getImmOrMaterializedImm()  local
1037     if (Def && Def->isMoveImmediate()) {  in getImmOrMaterializedImm()
1038       MachineOperand &ImmSrc = Def->getOperand(1);  in getImmOrMaterializedImm()
1375   MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());  in tryFoldClamp()  local
1378   if (TII->getClampMask(*Def) != TII->getClampMask(MI))  in tryFoldClamp()
1381   MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);  in tryFoldClamp()
1385   LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def);  in tryFoldClamp()
1389   MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());  in tryFoldClamp()
1514   MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());  in tryFoldOMod()  local
1515   MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);  in tryFoldOMod()
1521   if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))  in tryFoldOMod()
1524   LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def);  in tryFoldOMod()
1527   MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());  in tryFoldOMod()
1546   for (auto &Def : Defs) {  in tryFoldRegSequence()  local
1547     const auto *Op = Def.first;  in tryFoldRegSequence()
1593     MachineOperand *Def = Defs[I].first;  in tryFoldRegSequence()  local
1594     Def->setIsKill(false);  in tryFoldRegSequence()
1595     if (TRI->isAGPR(*MRI, Def->getReg())) {  in tryFoldRegSequence()
1596       RS.add(*Def);  in tryFoldRegSequence()
1598       MachineInstr *SubDef = MRI->getVRegDef(Def->getReg());  in tryFoldRegSequence()
1600       RS.addReg(SubDef->getOperand(1).getReg(), 0, Def->getSubReg());  in tryFoldRegSequence()
1676   MachineOperand &Def = MI.getOperand(0);  in tryFoldLoad()  local
1677   if (!Def.isDef())  in tryFoldLoad()
1680   Register DefReg = Def.getReg();  in tryFoldLoad()
1709   if (!TII->isOperandLegal(MI, 0, &Def)) {  in tryFoldLoad()