Lines Matching refs:getOpcode

35   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;  in isVector()
137 if (isALUInstr(MI.getOpcode())) in canBeConsideredALU()
139 if (isVector(MI) || isCubeOp(MI.getOpcode())) in canBeConsideredALU()
141 switch (MI.getOpcode()) { in canBeConsideredALU()
161 return isTransOnly(MI.getOpcode()); in isTransOnly()
169 return isVectorOnly(MI.getOpcode()); in isVectorOnly()
183 usesVertexCache(MI.getOpcode()); in usesVertexCache()
193 usesVertexCache(MI.getOpcode())) || in usesTextureCache()
194 usesTextureCache(MI.getOpcode()); in usesTextureCache()
216 if (!isALUInstr(MI.getOpcode())) { in readsLDSSrcReg()
258 if (MI.getOpcode() == R600::DOT_4) { in getSrcs()
272 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0])); in getSrcs()
276 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); in getSrcs()
292 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs()
299 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); in getSrcs()
305 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal)); in getSrcs()
525 unsigned Op = getOperandIdx(IG[i]->getOpcode(), in fitsReadPortLimitations()
591 if (!isALUInstr(MI.getOpcode())) in fitsConstReadLimitations()
634 if (isPredicateSetter(MI.getOpcode())) in findFirstPredicateSetterFrom()
665 if (isBranch(I->getOpcode())) in analyzeBranch()
667 if (!isJump(I->getOpcode())) { in analyzeBranch()
672 while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) { in analyzeBranch()
681 unsigned LastOpc = LastInst.getOpcode(); in analyzeBranch()
682 if (I == MBB.begin() || !isJump((--I)->getOpcode())) { in analyzeBranch()
688 while (!isPredicateSetter(predSet->getOpcode())) { in analyzeBranch()
702 unsigned SecondLastOpc = SecondLastInst.getOpcode(); in analyzeBranch()
707 while (!isPredicateSetter(predSet->getOpcode())) { in analyzeBranch()
726 if (It->getOpcode() == R600::CF_ALU || in FindLastAluClause()
727 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE) in FindLastAluClause()
758 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
774 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
793 switch (I->getOpcode()) { in removeBranch()
803 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
817 switch (I->getOpcode()) { in removeBranch()
828 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
860 if (MI.getOpcode() == R600::KILLGT) { in isPredicable()
862 } else if (MI.getOpcode() == R600::CF_ALU) { in isPredicable()
946 return isPredicateSetter(MI.getOpcode()); in ClobbersPredicate()
953 if (MI.getOpcode() == R600::CF_ALU) { in PredicateInstruction()
958 if (MI.getOpcode() == R600::DOT_4) { in PredicateInstruction()
1002 switch (MI.getOpcode()) { in expandPostRAPseudo()
1006 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr); in expandPostRAPseudo()
1011 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan); in expandPostRAPseudo()
1014 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst); in expandPostRAPseudo()
1028 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val); in expandPostRAPseudo()
1297 assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented"); in buildSlotOfVectorInstruction()
1305 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot))); in buildSlotOfVectorInstruction()
1307 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot))); in buildSlotOfVectorInstruction()
1327 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(), in buildSlotOfVectorInstruction()
1334 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot))); in buildSlotOfVectorInstruction()
1359 return getOperandIdx(MI.getOpcode(), Op); in getOperandIdx()
1380 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in getFlagOp()
1445 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in addFlag()
1466 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in clearFlag()