Lines Matching refs:R600TargetLowering
28 R600TargetLowering::R600TargetLowering(const TargetMachine &TM, in R600TargetLowering() function in R600TargetLowering
264 R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, in EmitInstrWithCustomInserter()
447 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
630 void R600TargetLowering::ReplaceNodeResults(SDNode *N, in ReplaceNodeResults()
672 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG, in vectorToVerticalVector()
687 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, in LowerEXTRACT_VECTOR_ELT()
702 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, in LowerINSERT_VECTOR_ELT()
719 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI, in LowerGlobalAddress()
734 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const { in LowerTrig()
768 SDValue R600TargetLowering::LowerShiftParts(SDValue Op, in LowerShiftParts()
775 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG, in LowerUADDSUBO()
793 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const { in lowerFP_TO_UINT()
803 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const { in lowerFP_TO_SINT()
813 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
828 bool R600TargetLowering::isZero(SDValue Op) const { in isZero()
838 bool R600TargetLowering::isHWTrueValue(SDValue Op) const { in isHWTrueValue()
845 bool R600TargetLowering::isHWFalseValue(SDValue Op) const { in isHWFalseValue()
852 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC()
998 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr, in stackPtrToRegIndex()
1020 void R600TargetLowering::getStackAddress(unsigned StackWidth, in getStackAddress()
1049 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store, in lowerPrivateTruncStore()
1139 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { in LowerSTORE()
1295 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op, in lowerPrivateExtLoad()
1351 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { in LowerLOAD()
1440 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { in LowerBRCOND()
1449 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op, in lowerFrameIndex()
1464 CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC, in CCAssignFnForCall()
1489 SDValue R600TargetLowering::LowerFormalArguments( in LowerFormalArguments()
1559 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType()
1566 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo()
1575 bool R600TargetLowering::allowsMisalignedMemoryAccesses( in allowsMisalignedMemoryAccesses()
1679 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], in OptimizeSwizzle()
1703 SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block, in constBufferLoad()
1753 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, in PerformDAGCombine()
1980 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, in FoldOperand()
2111 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, in PostISelFolding()