Lines Matching refs:MVT
31 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
32 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
44 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
45 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
50 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
51 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
52 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
53 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
55 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
56 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
57 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
59 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
60 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
61 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
66 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
67 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
69 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
70 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
71 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
73 setOperationAction(ISD::STORE, MVT::i8, Custom); in R600TargetLowering()
74 setOperationAction(ISD::STORE, MVT::i32, Custom); in R600TargetLowering()
75 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in R600TargetLowering()
76 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in R600TargetLowering()
78 setTruncStoreAction(MVT::i32, MVT::i8, Custom); in R600TargetLowering()
79 setTruncStoreAction(MVT::i32, MVT::i16, Custom); in R600TargetLowering()
82 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in R600TargetLowering()
83 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); in R600TargetLowering()
84 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Custom); in R600TargetLowering()
85 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom); in R600TargetLowering()
86 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()
87 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in R600TargetLowering()
88 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in R600TargetLowering()
89 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom); in R600TargetLowering()
90 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Custom); in R600TargetLowering()
91 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
94 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
95 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
98 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
99 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
100 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
101 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
102 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
103 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
104 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
105 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
106 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
107 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
108 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
109 setCondCodeAction(ISD::SETULE, MVT::f32, Expand); in R600TargetLowering()
111 setCondCodeAction(ISD::SETLE, MVT::i32, Expand); in R600TargetLowering()
112 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); in R600TargetLowering()
113 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); in R600TargetLowering()
114 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
116 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
117 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
119 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
120 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
122 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in R600TargetLowering()
123 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in R600TargetLowering()
124 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
126 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
128 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in R600TargetLowering()
129 setOperationAction(ISD::FTRUNC, MVT::f64, Custom); in R600TargetLowering()
130 setOperationAction(ISD::FRINT, MVT::f64, Custom); in R600TargetLowering()
131 setOperationAction(ISD::FFLOOR, MVT::f64, Custom); in R600TargetLowering()
133 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
134 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
136 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
137 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
138 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); in R600TargetLowering()
139 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom); in R600TargetLowering()
140 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
141 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in R600TargetLowering()
143 setOperationAction(ISD::SELECT, MVT::i32, Expand); in R600TargetLowering()
144 setOperationAction(ISD::SELECT, MVT::f32, Expand); in R600TargetLowering()
145 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); in R600TargetLowering()
146 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); in R600TargetLowering()
151 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
154 setOperationAction(ISD::USUBO, MVT::i32, Custom); in R600TargetLowering()
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
166 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
173 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
174 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand); in R600TargetLowering()
175 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand); in R600TargetLowering()
177 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
179 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
181 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
182 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
183 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
184 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
186 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
187 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
188 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
189 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
193 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in R600TargetLowering()
194 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in R600TargetLowering()
195 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in R600TargetLowering()
198 setOperationAction(ISD::FMA, MVT::f32, Expand); in R600TargetLowering()
199 setOperationAction(ISD::FMA, MVT::f64, Expand); in R600TargetLowering()
203 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
207 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in R600TargetLowering()
208 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in R600TargetLowering()
212 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in R600TargetLowering()
215 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in R600TargetLowering()
218 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
221 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
228 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
230 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in R600TargetLowering()
231 for (MVT VT : ScalarIntVTs) { in R600TargetLowering()
240 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); in R600TargetLowering()
241 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); in R600TargetLowering()
244 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in R600TargetLowering()
245 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in R600TargetLowering()
486 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
487 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
488 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
489 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
521 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
523 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
524 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
525 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
526 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
530 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
531 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
532 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
533 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
541 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
545 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
546 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
547 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
548 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
549 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
550 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
551 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
552 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
553 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
554 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
555 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
556 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
557 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
558 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
559 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
560 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
562 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
566 MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS); in LowerOperation()
638 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
647 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
728 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
745 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
746 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
760 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
765 DAG.getConstantFP(numbers::pif, DL, MVT::f32)); in LowerTrig()
786 DAG.getValueType(MVT::i1)); in LowerUADDSUBO()
798 MVT::i1, in lowerFP_TO_UINT()
799 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
808 MVT::i1, in lowerFP_TO_SINT()
809 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
824 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
863 if (VT == MVT::f32) { in LowerSELECT_CC()
902 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
972 if (CompareVT == MVT::f32) { in LowerSELECT_CC()
975 } else if (CompareVT == MVT::i32) { in LowerSELECT_CC()
1017 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1054 || Store->getValue().getValueType() == MVT::i8); in lowerPrivateTruncStore()
1058 if (Store->getMemoryVT() == MVT::i8) { in lowerPrivateTruncStore()
1060 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1061 } else if (Store->getMemoryVT() == MVT::i16) { in lowerPrivateTruncStore()
1063 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1078 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1083 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1084 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1089 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1094 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1095 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1098 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1099 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1103 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1110 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1114 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1118 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1121 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1124 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1133 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1161 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1188 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
1190 if (MemVT == MVT::i8) { in LowerSTORE()
1191 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1193 assert(MemVT == MVT::i16); in LowerSTORE()
1195 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1214 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1215 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1218 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1223 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) { in LowerSTORE()
1240 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1309 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1314 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1315 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1320 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1323 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1324 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1327 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1328 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1331 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1338 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1358 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1387 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1388 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1389 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1391 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1396 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1397 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1415 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1432 assert(VT == MVT::i32); in LowerLOAD()
1433 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1434 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1435 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1548 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1562 return MVT::i32; in getSetCCResultType()
1581 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
1584 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
1591 return VT.bitsGT(MVT::i32) && Alignment >= Align(4); in allowsMisalignedMemoryAccesses()
1616 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1619 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1689 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1697 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1712 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode)) in constBufferLoad()
1728 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1729 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1731 EVT NewVT = MVT::v4i32; in constBufferLoad()
1739 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1740 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1762 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1781 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1782 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1791 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1792 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
1993 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
1999 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2052 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32); in FoldOperand()
2060 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32); in FoldOperand()
2100 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2102 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()