Lines Matching refs:AMDGPU
25 using namespace llvm::AMDGPU;
155 if (AMDGPU::isGFX10Plus(STI)) { in printFlatOffset()
212 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
214 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
242 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
261 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
302 using namespace llvm::AMDGPU::MTBUFFormat; in printSymbolicFormat()
305 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
309 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
345 case AMDGPU::FP_REG: in printRegOperand()
346 case AMDGPU::SP_REG: in printRegOperand()
347 case AMDGPU::PRIVATE_RSRC_REG: in printRegOperand()
349 case AMDGPU::SCC: in printRegOperand()
391 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printVOPDst()
392 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printVOPDst()
393 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printVOPDst()
394 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printVOPDst()
395 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printVOPDst()
396 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printVOPDst()
397 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printVOPDst()
398 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printVOPDst()
399 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printVOPDst()
400 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printVOPDst()
401 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printVOPDst()
402 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printVOPDst()
410 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
456 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) { in printImmediate16()
499 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in printImmediate32()
533 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in printImmediate64()
579 printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? in printDefaultVccOperand()
580 AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI); in printDefaultVccOperand()
591 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in printOperand()
592 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) in printOperand()
606 case AMDGPU::OPERAND_REG_IMM_INT32: in printOperand()
607 case AMDGPU::OPERAND_REG_IMM_FP32: in printOperand()
608 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in printOperand()
609 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in printOperand()
610 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in printOperand()
611 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in printOperand()
612 case AMDGPU::OPERAND_REG_IMM_V2INT32: in printOperand()
613 case AMDGPU::OPERAND_REG_IMM_V2FP32: in printOperand()
614 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in printOperand()
615 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in printOperand()
619 case AMDGPU::OPERAND_REG_IMM_INT64: in printOperand()
620 case AMDGPU::OPERAND_REG_IMM_FP64: in printOperand()
621 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in printOperand()
622 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in printOperand()
623 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in printOperand()
626 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in printOperand()
627 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in printOperand()
628 case AMDGPU::OPERAND_REG_IMM_INT16: in printOperand()
631 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in printOperand()
632 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in printOperand()
633 case AMDGPU::OPERAND_REG_IMM_FP16: in printOperand()
636 case AMDGPU::OPERAND_REG_IMM_V2INT16: in printOperand()
637 case AMDGPU::OPERAND_REG_IMM_V2FP16: in printOperand()
639 STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { in printOperand()
645 if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) { in printOperand()
650 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in printOperand()
651 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in printOperand()
654 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in printOperand()
655 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in printOperand()
680 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()
699 case AMDGPU::V_CNDMASK_B32_e32_gfx10: in printOperand()
700 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printOperand()
701 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printOperand()
702 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printOperand()
703 case AMDGPU::V_CNDMASK_B32_dpp_gfx10: in printOperand()
704 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printOperand()
705 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printOperand()
706 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printOperand()
707 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10: in printOperand()
708 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printOperand()
709 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printOperand()
710 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printOperand()
712 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: in printOperand()
713 case AMDGPU::V_CNDMASK_B32_e32_vi: in printOperand()
714 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printOperand()
715 AMDGPU::OpName::src1)) in printOperand()
722 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printOperand()
779 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10: in printOperandAndIntInputMods()
780 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
781 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
782 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
783 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printOperandAndIntInputMods()
784 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
793 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
807 using namespace AMDGPU::DPP; in printDPPCtrl()
811 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printDPPCtrl()
812 AMDGPU::OpName::src0); in printDPPCtrl()
815 Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID && in printDPPCtrl()
816 !AMDGPU::isLegal64BitDPPControl(Imm)) { in printDPPCtrl()
838 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
844 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
850 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
856 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
866 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
872 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
879 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
881 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
891 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
928 using namespace llvm::AMDGPU::DPP; in printFI()
937 using namespace llvm::AMDGPU::SDWA; in printSDWASel()
976 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
992 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
995 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1034 using namespace llvm::AMDGPU::Exp; in printExpTgt()
1073 for (int OpName : { AMDGPU::OpName::src0_modifiers, in printPackedModifier()
1074 AMDGPU::OpName::src1_modifiers, in printPackedModifier()
1075 AMDGPU::OpName::src2_modifiers }) { in printPackedModifier()
1076 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); in printPackedModifier()
1113 if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 || in printOpSel()
1114 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) { in printOpSel()
1115 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOpSel()
1116 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); in printOpSel()
1181 using namespace llvm::AMDGPU::VGPRIndexMode; in printVGPRIndexMode()
1256 using namespace llvm::AMDGPU::SendMsg; in printSendMsg()
1287 using namespace llvm::AMDGPU::Swizzle; in printSwizzleBitmask()
1319 using namespace llvm::AMDGPU::Swizzle; in printSwizzle()
1392 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printWaitFlag()
1425 using namespace llvm::AMDGPU::Hwreg; in printHwreg()