Lines Matching refs:AMDGPUAsmBackend
26 class AMDGPUAsmBackend : public MCAsmBackend { class
28 AMDGPUAsmBackend(const Target &T) : MCAsmBackend(support::little) {} in AMDGPUAsmBackend() function in __anoncabfcc730111::AMDGPUAsmBackend
54 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst, in relaxInstruction()
63 bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, in fixupNeedsRelaxation()
73 bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst, in mayNeedRelaxation()
131 void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, in applyFixup()
155 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( in getFixupKindInfo()
168 unsigned AMDGPUAsmBackend::getMinimumNopSize() const { in getMinimumNopSize()
172 bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { in writeNopData()
197 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
205 AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn), in ELFAMDGPUAsmBackend()