64                               RegSubRegPair CombOldVGPR,
69                               RegSubRegPair CombOldVGPR, bool CombBCZ,
182                                            RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
210           CombOldVGPR,  in createDPPInst()
214       auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);  in createDPPInst()
215       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,  in createDPPInst()
216                      CombOldVGPR.SubReg);  in createDPPInst()
348     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
350   assert(CombOldVGPR.Reg);  in createDPPInst()
361     CombOldVGPR = getRegSubRegPair(*Src1);  in createDPPInst()
364     if (!isOfRegClass(CombOldVGPR, *RC, *MRI)) {  in createDPPInst()
369   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);  in createDPPInst()
478   auto CombOldVGPR = getRegSubRegPair(*OldOpnd);  in combineDPPMov()  local
482     CombOldVGPR = RegSubRegPair(  in combineDPPMov()
485                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
559       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,  in combineDPPMov()
572                 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,  in combineDPPMov()