126   if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {  in isShrinkable()
135   if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||  in isShrinkable()
136       !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||  in isShrinkable()
137       !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) ||  in isShrinkable()
138       !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) {  in isShrinkable()
146   auto DPP32 = AMDGPU::getDPPOp32(Op);  in getDPPOp()
149     auto E32 = AMDGPU::getVOPe32(Op);  in getDPPOp()
150     DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32);  in getDPPOp()
166   case AMDGPU::IMPLICIT_DEF:  in getOldOpndValue()
168   case AMDGPU::COPY:  in getOldOpndValue()
169   case AMDGPU::V_MOV_B32_e32:  in getOldOpndValue()
170   case AMDGPU::V_MOV_B64_PSEUDO: {  in getOldOpndValue()
185   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp ||  in createDPPInst()
186          MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);  in createDPPInst()
201     auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);  in createDPPInst()
206     const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);  in createDPPInst()
212               TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()),  in createDPPInst()
227                                           AMDGPU::OpName::src0_modifiers)) {  in createDPPInst()
228       assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,  in createDPPInst()
229                                           AMDGPU::OpName::src0_modifiers));  in createDPPInst()
233     } else if (AMDGPU::getNamedOperandIdx(DPPOp,  in createDPPInst()
234                    AMDGPU::OpName::src0_modifiers) != -1) {  in createDPPInst()
238     auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in createDPPInst()
250                                           AMDGPU::OpName::src1_modifiers)) {  in createDPPInst()
251       assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,  in createDPPInst()
252                                           AMDGPU::OpName::src1_modifiers));  in createDPPInst()
256     } else if (AMDGPU::getNamedOperandIdx(DPPOp,  in createDPPInst()
257                    AMDGPU::OpName::src1_modifiers) != -1) {  in createDPPInst()
261     if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {  in createDPPInst()
271     if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {  in createDPPInst()
272       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||  in createDPPInst()
281     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));  in createDPPInst()
282     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));  in createDPPInst()
283     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));  in createDPPInst()
299   case AMDGPU::V_ADD_U32_e32:  in isIdentityValue()
300   case AMDGPU::V_ADD_U32_e64:  in isIdentityValue()
301   case AMDGPU::V_ADD_CO_U32_e32:  in isIdentityValue()
302   case AMDGPU::V_ADD_CO_U32_e64:  in isIdentityValue()
303   case AMDGPU::V_OR_B32_e32:  in isIdentityValue()
304   case AMDGPU::V_OR_B32_e64:  in isIdentityValue()
305   case AMDGPU::V_SUBREV_U32_e32:  in isIdentityValue()
306   case AMDGPU::V_SUBREV_U32_e64:  in isIdentityValue()
307   case AMDGPU::V_SUBREV_CO_U32_e32:  in isIdentityValue()
308   case AMDGPU::V_SUBREV_CO_U32_e64:  in isIdentityValue()
309   case AMDGPU::V_MAX_U32_e32:  in isIdentityValue()
310   case AMDGPU::V_MAX_U32_e64:  in isIdentityValue()
311   case AMDGPU::V_XOR_B32_e32:  in isIdentityValue()
312   case AMDGPU::V_XOR_B32_e64:  in isIdentityValue()
316   case AMDGPU::V_AND_B32_e32:  in isIdentityValue()
317   case AMDGPU::V_AND_B32_e64:  in isIdentityValue()
318   case AMDGPU::V_MIN_U32_e32:  in isIdentityValue()
319   case AMDGPU::V_MIN_U32_e64:  in isIdentityValue()
324   case AMDGPU::V_MIN_I32_e32:  in isIdentityValue()
325   case AMDGPU::V_MIN_I32_e64:  in isIdentityValue()
330   case AMDGPU::V_MAX_I32_e32:  in isIdentityValue()
331   case AMDGPU::V_MAX_I32_e64:  in isIdentityValue()
336   case AMDGPU::V_MUL_I32_I24_e32:  in isIdentityValue()
337   case AMDGPU::V_MUL_I32_I24_e64:  in isIdentityValue()
338   case AMDGPU::V_MUL_U32_U24_e32:  in isIdentityValue()
339   case AMDGPU::V_MUL_U32_U24_e64:  in isIdentityValue()
352     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
362     auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in createDPPInst()
385   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp ||  in combineDPPMov()
386          MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);  in combineDPPMov()
389   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in combineDPPMov()
402   if (MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) {  in combineDPPMov()
403     auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl);  in combineDPPMov()
405     if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) {  in combineDPPMov()
413   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);  in combineDPPMov()
415   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);  in combineDPPMov()
420   auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);  in combineDPPMov()
424   auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);  in combineDPPMov()
425   auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in combineDPPMov()
485                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
505     if (OrigOp == AMDGPU::REG_SEQUENCE) {  in combineDPPMov()
540     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);  in combineDPPMov()
541     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in combineDPPMov()
617       if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {  in runOnMachineFunction()
620       } else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) {  in runOnMachineFunction()