646       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),  in convertSDWAInst()
832 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {  in createRegOperand()  function in AMDGPUDisassembler
837 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,  in createRegOperand()  function in AMDGPUDisassembler
843   return createRegOperand(RegCl.getRegister(Val));  in createRegOperand()
883   return createRegOperand(SRegClassID, Val >> shift);  in createSRegOperand()
916   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);  in decodeOperand_VGPR_32()
924   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);  in decodeOperand_AGPR_32()
928   return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255);  in decodeOperand_AReg_64()
932   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);  in decodeOperand_AReg_128()
936   return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255);  in decodeOperand_AReg_256()
940   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);  in decodeOperand_AReg_512()
944   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);  in decodeOperand_AReg_1024()
956   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);  in decodeOperand_VReg_64()
960   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);  in decodeOperand_VReg_96()
964   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);  in decodeOperand_VReg_128()
968   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);  in decodeOperand_VReg_256()
972   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);  in decodeOperand_VReg_512()
976   return createRegOperand(AMDGPU::VReg_1024RegClassID, Val);  in decodeOperand_VReg_1024()
1247     return createRegOperand(IsAGPR ? getAgprClassId(Width)  in decodeSrcOp()
1307   case 102: return createRegOperand(FLAT_SCR_LO);  in decodeSpecialReg32()
1308   case 103: return createRegOperand(FLAT_SCR_HI);  in decodeSpecialReg32()
1309   case 104: return createRegOperand(XNACK_MASK_LO);  in decodeSpecialReg32()
1310   case 105: return createRegOperand(XNACK_MASK_HI);  in decodeSpecialReg32()
1311   case 106: return createRegOperand(VCC_LO);  in decodeSpecialReg32()
1312   case 107: return createRegOperand(VCC_HI);  in decodeSpecialReg32()
1313   case 108: return createRegOperand(TBA_LO);  in decodeSpecialReg32()
1314   case 109: return createRegOperand(TBA_HI);  in decodeSpecialReg32()
1315   case 110: return createRegOperand(TMA_LO);  in decodeSpecialReg32()
1316   case 111: return createRegOperand(TMA_HI);  in decodeSpecialReg32()
1317   case 124: return createRegOperand(M0);  in decodeSpecialReg32()
1318   case 125: return createRegOperand(SGPR_NULL);  in decodeSpecialReg32()
1319   case 126: return createRegOperand(EXEC_LO);  in decodeSpecialReg32()
1320   case 127: return createRegOperand(EXEC_HI);  in decodeSpecialReg32()
1321   case 235: return createRegOperand(SRC_SHARED_BASE);  in decodeSpecialReg32()
1322   case 236: return createRegOperand(SRC_SHARED_LIMIT);  in decodeSpecialReg32()
1323   case 237: return createRegOperand(SRC_PRIVATE_BASE);  in decodeSpecialReg32()
1324   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);  in decodeSpecialReg32()
1325   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);  in decodeSpecialReg32()
1326   case 251: return createRegOperand(SRC_VCCZ);  in decodeSpecialReg32()
1327   case 252: return createRegOperand(SRC_EXECZ);  in decodeSpecialReg32()
1328   case 253: return createRegOperand(SRC_SCC);  in decodeSpecialReg32()
1329   case 254: return createRegOperand(LDS_DIRECT);  in decodeSpecialReg32()
1339   case 102: return createRegOperand(FLAT_SCR);  in decodeSpecialReg64()
1340   case 104: return createRegOperand(XNACK_MASK);  in decodeSpecialReg64()
1341   case 106: return createRegOperand(VCC);  in decodeSpecialReg64()
1342   case 108: return createRegOperand(TBA);  in decodeSpecialReg64()
1343   case 110: return createRegOperand(TMA);  in decodeSpecialReg64()
1344   case 125: return createRegOperand(SGPR_NULL);  in decodeSpecialReg64()
1345   case 126: return createRegOperand(EXEC);  in decodeSpecialReg64()
1346   case 235: return createRegOperand(SRC_SHARED_BASE);  in decodeSpecialReg64()
1347   case 236: return createRegOperand(SRC_SHARED_LIMIT);  in decodeSpecialReg64()
1348   case 237: return createRegOperand(SRC_PRIVATE_BASE);  in decodeSpecialReg64()
1349   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);  in decodeSpecialReg64()
1350   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);  in decodeSpecialReg64()
1351   case 251: return createRegOperand(SRC_VCCZ);  in decodeSpecialReg64()
1352   case 252: return createRegOperand(SRC_EXECZ);  in decodeSpecialReg64()
1353   case 253: return createRegOperand(SRC_SCC);  in decodeSpecialReg64()
1370       return createRegOperand(getVgprClassId(Width),  in decodeSDWASrc()
1395     return createRegOperand(getVgprClassId(Width), Val);  in decodeSDWASrc()
1431     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);  in decodeSDWAVopcDst()