Lines Matching refs:AMDGPUDisassembler
41 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, in AMDGPUDisassembler() function in AMDGPUDisassembler
73 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeSoppBrTarget()
87 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeSMEMOffset()
99 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeBoolReg()
108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
151 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in DECODE_OPERAND_REG()
159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VSrcV216()
167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VSrcV232()
175 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VS_16()
183 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VS_32()
191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_AReg_64()
192 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); in decodeOperand_AReg_64()
199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_AReg_128()
200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); in decodeOperand_AReg_128()
207 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_AReg_256()
208 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); in decodeOperand_AReg_256()
215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_AReg_512()
216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); in decodeOperand_AReg_512()
223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_AReg_1024()
224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); in decodeOperand_AReg_1024()
231 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VReg_64()
232 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); in decodeOperand_VReg_64()
239 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VReg_128()
240 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); in decodeOperand_VReg_128()
247 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VReg_256()
248 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); in decodeOperand_VReg_256()
255 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VReg_512()
256 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); in decodeOperand_VReg_512()
263 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VReg_1024()
264 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); in decodeOperand_VReg_1024()
283 AMDGPUDisassembler::OpWidthTy Opw, in decodeOperand_AVLdSt_Any()
285 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_AVLdSt_Any()
321 AMDGPUDisassembler::OPW32, Decoder); in DecodeAVLdSt_32RegisterClass()
329 AMDGPUDisassembler::OPW64, Decoder); in DecodeAVLdSt_64RegisterClass()
337 AMDGPUDisassembler::OPW96, Decoder); in DecodeAVLdSt_96RegisterClass()
345 AMDGPUDisassembler::OPW128, Decoder); in DecodeAVLdSt_128RegisterClass()
352 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_SReg_32()
360 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); in decodeOperand_VGPR_32()
361 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); in decodeOperand_VGPR_32()
384 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, in tryDecodeInst()
414 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, in getInstruction()
636 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { in convertSDWAInst()
658 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { in convertDPP8Inst()
679 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { in convertMIMGInst()
816 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
822 MCOperand AMDGPUDisassembler::errOperand(unsigned V, in errOperand()
832 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { in createRegOperand()
837 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
847 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, in createSRegOperand()
886 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
890 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
894 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { in decodeOperand_VS_128()
898 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { in decodeOperand_VSrc16()
902 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { in decodeOperand_VSrcV216()
906 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { in decodeOperand_VSrcV232()
910 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
919 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { in decodeOperand_VRegOrLds_32()
923 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { in decodeOperand_AGPR_32()
927 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { in decodeOperand_AReg_64()
931 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { in decodeOperand_AReg_128()
935 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { in decodeOperand_AReg_256()
939 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { in decodeOperand_AReg_512()
943 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { in decodeOperand_AReg_1024()
947 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { in decodeOperand_AV_32()
951 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { in decodeOperand_AV_64()
955 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { in decodeOperand_VReg_64()
959 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { in decodeOperand_VReg_96()
963 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { in decodeOperand_VReg_128()
967 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { in decodeOperand_VReg_256()
971 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { in decodeOperand_VReg_512()
975 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { in decodeOperand_VReg_1024()
979 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { in decodeOperand_SReg_32()
986 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( in decodeOperand_SReg_32_XM0_XEXEC()
992 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( in decodeOperand_SReg_32_XEXEC_HI()
998 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { in decodeOperand_SRegOrLds_32()
1005 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { in decodeOperand_SReg_64()
1009 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { in decodeOperand_SReg_64_XEXEC()
1013 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { in decodeOperand_SReg_128()
1017 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { in decodeOperand_SReg_256()
1021 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { in decodeOperand_SReg_512()
1025 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { in decodeLiteralConstant()
1040 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { in decodeIntImmed()
1125 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { in decodeFPImmed()
1148 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { in getVgprClassId()
1169 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { in getAgprClassId()
1191 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { in getSgprClassId()
1211 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { in getTtmpClassId()
1229 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { in getTTmpIdx()
1238 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { in decodeSrcOp()
1283 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { in decodeDstOp()
1303 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { in decodeSpecialReg32()
1335 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { in decodeSpecialReg64()
1359 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, in decodeSDWASrc()
1400 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { in decodeSDWASrc16()
1404 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { in decodeSDWASrc32()
1408 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { in decodeSDWAVopcDst()
1435 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { in decodeBoolReg()
1440 bool AMDGPUDisassembler::isVI() const { in isVI()
1444 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } in isGFX9()
1446 bool AMDGPUDisassembler::isGFX90A() const { in isGFX90A()
1450 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } in isGFX9Plus()
1452 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } in isGFX10()
1454 bool AMDGPUDisassembler::isGFX10Plus() const { in isGFX10Plus()
1458 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { in hasArchitectedFlatScratch()
1472 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( in decodeCOMPUTE_PGM_RSRC1()
1569 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( in decodeCOMPUTE_PGM_RSRC2()
1625 AMDGPUDisassembler::decodeKernelDescriptorDirective( in decodeKernelDescriptorDirective()
1769 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( in decodeKernelDescriptor()
1795 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, in onSymbolStart()
1874 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); in createAMDGPUDisassembler()