1259   void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1261   void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
1430                                OperandVector &Operands, MCStreamer &Out,
1434   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic,
1438                         SMLoc NameLoc, OperandVector &Operands) override;
1444   parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1450                               OperandVector &Operands,
1455   parseNamedBit(StringRef Name, OperandVector &Operands,
1457   OperandMatchResultTy parseCPol(OperandVector &Operands);
1468   OperandMatchResultTy parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);
1469   OperandMatchResultTy parseReg(OperandVector &Operands);
1470   OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);
1471   OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm = true);
1472   OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm = true);
1473   OperandMatchResultTy parseRegWithFPInputMods(OperandVector &Operands);
1474   OperandMatchResultTy parseRegWithIntInputMods(OperandVector &Operands);
1475   OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands);
1480   OperandMatchResultTy parseFORMAT(OperandVector &Operands);
1486   void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
1487   void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); }  in cvtDS()  argument
1488   void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); }  in cvtDSGds()  argument
1489   void cvtExp(MCInst &Inst, const OperandVector &Operands);
1492   OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
1493   OperandMatchResultTy parseHwreg(OperandVector &Operands);
1517   SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
1518   SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
1521                       const OperandVector &Operands) const;
1522   SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
1523   SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
1524   SMLoc getLitLoc(const OperandVector &Operands) const;
1525   SMLoc getConstLoc(const OperandVector &Operands) const;
1527   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1528   bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1529   bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
1531   bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
1532   bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector &Operands);
1536   bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
1543   bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
1545   bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands);
1546   bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
1549   bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
1551   bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
1580   bool parseExpr(OperandVector &Operands);
1590   OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
1591   OperandMatchResultTy parseOptionalOpr(OperandVector &Operands);
1593   OperandMatchResultTy parseExpTgt(OperandVector &Operands);
1594   OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
1595   OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
1596   OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
1597   OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
1598   OperandMatchResultTy parseBoolReg(OperandVector &Operands);
1609   OperandMatchResultTy parseSwizzleOp(OperandVector &Operands);
1618   OperandMatchResultTy parseGPRIdxMode(OperandVector &Operands);
1621 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }  in cvtMubuf()  argument
1622 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr…  in cvtMubufAtomic()  argument
1623 …void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false…  in cvtMubufLds()  argument
1624   void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
1633   OperandMatchResultTy parseOModOperand(OperandVector &Operands);
1635   void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1637   void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1638   void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1639   void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1640   void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
1643   void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1645   void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
1647   void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
1648   void cvtIntersectRay(MCInst &Inst, const OperandVector &Operands);
1650   void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);
1653   OperandMatchResultTy parseDim(OperandVector &Operands);
1654   OperandMatchResultTy parseDPP8(OperandVector &Operands);
1655   OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
1656   bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
1663   void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1664   void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); }  in cvtDPP8()  argument
1666   OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
1668   OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
1669   void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1670   void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1671   void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1672   void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1673   void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1674   void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1683   OperandMatchResultTy parseEndpgmOp(OperandVector &Operands);
2736 AMDGPUAsmParser::parseImm(OperandVector &Operands, bool HasSP3AbsModifier) {  in parseImm()  argument
2770     Operands.push_back(  in parseImm()
2798       Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));  in parseImm()
2800       Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));  in parseImm()
2810 AMDGPUAsmParser::parseReg(OperandVector &Operands) {  in parseReg()  argument
2816     Operands.push_back(std::move(R));  in parseReg()
2823 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod) {  in parseRegOrImm()  argument
2824   auto res = parseReg(Operands);  in parseRegOrImm()
2830     return parseImm(Operands, HasSP3AbsMod);  in parseRegOrImm()
2925 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,  in parseRegOrImmWithFPInputMods()  argument
2961     Res = parseRegOrImm(Operands, SP3Abs);  in parseRegOrImmWithFPInputMods()
2963     Res = parseReg(Operands);  in parseRegOrImmWithFPInputMods()
2981     AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());  in parseRegOrImmWithFPInputMods()
2992 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,  in parseRegOrImmWithIntInputMods()  argument
3000     Res = parseRegOrImm(Operands);  in parseRegOrImmWithIntInputMods()
3002     Res = parseReg(Operands);  in parseRegOrImmWithIntInputMods()
3015     AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());  in parseRegOrImmWithIntInputMods()
3027 AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {  in parseRegWithFPInputMods()  argument
3028   return parseRegOrImmWithFPInputMods(Operands, false);  in parseRegWithFPInputMods()
3032 AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {  in parseRegWithIntInputMods()  argument
3033   return parseRegOrImmWithIntInputMods(Operands, false);  in parseRegWithIntInputMods()
3036 OperandMatchResultTy AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {  in parseVReg32OrOff()  argument
3039     Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,  in parseVReg32OrOff()
3049     Operands.push_back(std::move(Reg));  in parseVReg32OrOff()
3238                                                 const OperandVector &Operands) {  in validateConstantBusLimitations()  argument
3318   SMLoc LitLoc = getLitLoc(Operands);  in validateConstantBusLimitations()
3319   SMLoc RegLoc = getRegLoc(LastSGPR, Operands);  in validateConstantBusLimitations()
3327                                                  const OperandVector &Operands) {  in validateEarlyClobberLimitations()  argument
3356         Error(getRegLoc(SrcReg, Operands),  in validateEarlyClobberLimitations()
3540                                       const OperandVector &Operands) {  in validateMovrels()  argument
3558     ErrLoc = getRegLoc(Reg, Operands);  in validateMovrels()
3560     ErrLoc = getConstLoc(Operands);  in validateMovrels()
3568                                           const OperandVector &Operands) {  in validateMAIAccWrite()  argument
3585     Error(getRegLoc(Reg, Operands),  in validateMAIAccWrite()
3818 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {  in getFlatOffsetLoc()
3819   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in getFlatOffsetLoc()
3820     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in getFlatOffsetLoc()
3828                                          const OperandVector &Operands) {  in validateFlatOffset()  argument
3839     Error(getFlatOffsetLoc(Operands),  in validateFlatOffset()
3849       Error(getFlatOffsetLoc(Operands),  in validateFlatOffset()
3856       Error(getFlatOffsetLoc(Operands),  in validateFlatOffset()
3865 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {  in getSMEMOffsetLoc()
3867   for (unsigned i = 2, e = Operands.size(); i != e; ++i) {  in getSMEMOffsetLoc()
3868     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in getSMEMOffsetLoc()
3876                                          const OperandVector &Operands) {  in validateSMEMOffset()  argument
3899   Error(getSMEMOffsetLoc(Operands),  in validateSMEMOffset()
3956                                   const OperandVector &Operands) {  in validateDPP()  argument
3968       SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);  in validateDPP()
3986                                           const OperandVector &Operands) {  in validateVOP3Literal()  argument
4013       Error(getConstLoc(Operands),  in validateVOP3Literal()
4034     Error(getLitLoc(Operands), "literal operands are not supported");  in validateVOP3Literal()
4039     Error(getLitLoc(Operands), "only one literal operand is allowed");  in validateVOP3Literal()
4122                                   const OperandVector &Operands) {  in validateGWS()  argument
4139     SMLoc RegLoc = getRegLoc(Reg, Operands);  in validateGWS()
4148                                             const OperandVector &Operands,  in validateCoherencyBits()  argument
4165     SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);  in validateCoherencyBits()
4182       SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);  in validateCoherencyBits()
4195                                           const OperandVector &Operands) {  in validateInstruction()  argument
4197     Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);  in validateInstruction()
4201     Error(getLitLoc(Operands),  in validateInstruction()
4205   if (!validateVOP3Literal(Inst, Operands)) {  in validateInstruction()
4208   if (!validateConstantBusLimitations(Inst, Operands)) {  in validateInstruction()
4211   if (!validateEarlyClobberLimitations(Inst, Operands)) {  in validateInstruction()
4215     Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),  in validateInstruction()
4220     Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),  in validateInstruction()
4224   if (!validateDPP(Inst, Operands)) {  in validateInstruction()
4229     Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),  in validateInstruction()
4238     Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),  in validateInstruction()
4253     Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),  in validateInstruction()
4258     Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),  in validateInstruction()
4262   if (!validateMovrels(Inst, Operands)) {  in validateInstruction()
4265   if (!validateFlatOffset(Inst, Operands)) {  in validateInstruction()
4268   if (!validateSMEMOffset(Inst, Operands)) {  in validateInstruction()
4271   if (!validateMAIAccWrite(Inst, Operands)) {  in validateInstruction()
4274   if (!validateCoherencyBits(Inst, Operands, IDLoc)) {  in validateInstruction()
4290   if (!validateGWS(Inst, Operands)) {  in validateInstruction()
4298   if (!validateCoherencyBits(Inst, Operands, IDLoc)) {  in validateInstruction()
4361                                               OperandVector &Operands,  in MatchAndEmitInstruction()  argument
4369     auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,  in MatchAndEmitInstruction()
4390     if (!validateInstruction(Inst, IDLoc, Operands)) {  in MatchAndEmitInstruction()
4398   StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();  in MatchAndEmitInstruction()
4414       if (ErrorInfo >= Operands.size()) {  in MatchAndEmitInstruction()
4417       ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();  in MatchAndEmitInstruction()
5301 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic,  in parseOperand()  argument
5304   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);  in parseOperand()
5319     unsigned Prefix = Operands.size();  in parseOperand()
5323       ResTy = parseReg(Operands);  in parseOperand()
5339     if (Operands.size() - Prefix > 1) {  in parseOperand()
5340       Operands.insert(Operands.begin() + Prefix,  in parseOperand()
5342       Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));  in parseOperand()
5348   return parseRegOrImm(Operands);  in parseOperand()
5375                                        SMLoc NameLoc, OperandVector &Operands) {  in ParseInstruction()  argument
5378   Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));  in ParseInstruction()
5384     if (IsMIMG && isGFX10Plus() && Operands.size() == 2)  in ParseInstruction()
5387     OperandMatchResultTy Res = parseOperand(Operands, Name, Mode);  in ParseInstruction()
5425 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,  in parseIntWithPrefix()  argument
5439   Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));  in parseIntWithPrefix()
5445                                              OperandVector &Operands,  in parseOperandArrayWithPrefix()  argument
5485   Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));  in parseOperandArrayWithPrefix()
5490 AMDGPUAsmParser::parseNamedBit(StringRef Name, OperandVector &Operands,  in parseNamedBit()  argument
5515   Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));  in parseNamedBit()
5520 AMDGPUAsmParser::parseCPol(OperandVector &Operands) {  in parseCPol()  argument
5561   for (unsigned I = 1; I != Operands.size(); ++I) {  in parseCPol()
5562     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in parseCPol()
5569   Operands.push_back(AMDGPUOperand::CreateImm(this, CPolOn, S,  in parseCPol()
5576   MCInst& Inst, const OperandVector& Operands,  in addOptionalImmOperand()  argument
5583     ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);  in addOptionalImmOperand()
5807 AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {  in parseFORMAT()  argument
5821   Operands.push_back(  in parseFORMAT()
5834   Res = parseRegOrImm(Operands);  in parseFORMAT()
5845       auto Size = Operands.size();  in parseFORMAT()
5846       AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]);  in parseFORMAT()
5865                                     const OperandVector &Operands) {  in cvtDSOffset01()  argument
5868   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtDSOffset01()
5869     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtDSOffset01()
5881   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0);  in cvtDSOffset01()
5882   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1);  in cvtDSOffset01()
5883   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);  in cvtDSOffset01()
5888 void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,  in cvtDSImpl()  argument
5892   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtDSImpl()
5893     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtDSImpl()
5916   addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType);  in cvtDSImpl()
5919     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);  in cvtDSImpl()
5924 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {  in cvtExp()  argument
5931   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtExp()
5932     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtExp()
5979   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);  in cvtExp()
5980   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);  in cvtExp()
6060 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {  in parseSWaitCntOps()  argument
6075   Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));  in parseSWaitCntOps()
6153 AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {  in parseHwreg()  argument
6178   Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg));  in parseHwreg()
6264 AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {  in parseSendMsgOp()  argument
6289   Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));  in parseSendMsgOp()
6301 OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {  in parseInterpSlot()  argument
6319   Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,  in parseInterpSlot()
6324 OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {  in parseInterpAttr()  argument
6363   Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,  in parseInterpAttr()
6365   Operands.push_back(AMDGPUOperand::CreateImm(this, AttrChan, SChan,  in parseInterpAttr()
6374 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {  in parseExpTgt()  argument
6391   Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,  in parseExpTgt()
6486 AMDGPUAsmParser::parseExpr(OperandVector &Operands) {  in parseExpr()  argument
6495     Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));  in parseExpr()
6497     Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));  in parseExpr()
6567                                const OperandVector &Operands) const {  in getOperandLoc()
6568   for (unsigned i = Operands.size() - 1; i > 0; --i) {  in getOperandLoc()
6569     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in getOperandLoc()
6573   return ((AMDGPUOperand &)*Operands[0]).getStartLoc();  in getOperandLoc()
6578                            const OperandVector &Operands) const {  in getImmLoc()
6580   return getOperandLoc(Test, Operands);  in getImmLoc()
6585                            const OperandVector &Operands) const {  in getRegLoc()
6589   return getOperandLoc(Test, Operands);  in getRegLoc()
6593 AMDGPUAsmParser::getLitLoc(const OperandVector &Operands) const {  in getLitLoc()
6597   return getOperandLoc(Test, Operands);  in getLitLoc()
6601 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {  in getConstLoc()
6605   return getOperandLoc(Test, Operands);  in getConstLoc()
6840 AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {  in parseSwizzleOp()  argument
6855     Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));  in parseSwizzleOp()
6861     return parseOptionalOpr(Operands);  in parseSwizzleOp()
6919 AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {  in parseGPRIdxMode()  argument
6939   Operands.push_back(  in parseGPRIdxMode()
6953 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {  in parseSOppBrTarget()  argument
6961   if (!parseExpr(Operands))  in parseSOppBrTarget()
6964   AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);  in parseSOppBrTarget()
6984 AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {  in parseBoolReg()  argument
6985   return parseReg(Operands);  in parseBoolReg()
6997                                    const OperandVector &Operands,  in cvtMubufImpl()  argument
7007     for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {  in cvtMubufImpl()
7008       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtMubufImpl()
7025   for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {  in cvtMubufImpl()
7026     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtMubufImpl()
7073   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);  in cvtMubufImpl()
7074   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);  in cvtMubufImpl()
7077     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);  in cvtMubufImpl()
7079   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySWZ);  in cvtMubufImpl()
7082 void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {  in cvtMtbuf()  argument
7085   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtMtbuf()
7086     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtMtbuf()
7111   addOptionalImmOperand(Inst, Operands, OptionalIdx,  in cvtMtbuf()
7113   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyFORMAT);  in cvtMtbuf()
7114   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);  in cvtMtbuf()
7115   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);  in cvtMtbuf()
7116   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySWZ);  in cvtMtbuf()
7123 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,  in cvtMIMG()  argument
7128     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtMIMG()
7134     ((AMDGPUOperand &)*Operands[I - 1]).addRegOperands(Inst, 1);  in cvtMIMG()
7139   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtMIMG()
7140     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtMIMG()
7154   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);  in cvtMIMG()
7156     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDim, -1);  in cvtMIMG()
7157   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);  in cvtMIMG()
7158   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol);  in cvtMIMG()
7159   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);  in cvtMIMG()
7161     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16);  in cvtMIMG()
7163     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);  in cvtMIMG()
7164   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);  in cvtMIMG()
7166     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);  in cvtMIMG()
7167   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16);  in cvtMIMG()
7170 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {  in cvtMIMGAtomic()  argument
7171   cvtMIMG(Inst, Operands, true);  in cvtMIMGAtomic()
7174 void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {  in cvtSMEMAtomic()  argument
7178   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtSMEMAtomic()
7179     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtSMEMAtomic()
7195   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtSMEMAtomic()
7196     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtSMEMAtomic()
7225     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);  in cvtSMEMAtomic()
7226   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);  in cvtSMEMAtomic()
7230                                       const OperandVector &Operands) {  in cvtIntersectRay()  argument
7231   for (unsigned I = 1; I < Operands.size(); ++I) {  in cvtIntersectRay()
7232     auto &Operand = (AMDGPUOperand &)*Operands[I];  in cvtIntersectRay()
7368 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {  in parseOptionalOperand()  argument
7370   OperandMatchResultTy res = parseOptionalOpr(Operands);  in parseOptionalOperand()
7389     res = parseOptionalOpr(Operands);  in parseOptionalOperand()
7395 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands) {  in parseOptionalOpr()  argument
7400       res = parseNamedBit(Op.Name, Operands, Op.Type);  in parseOptionalOpr()
7402       res = parseOModOperand(Operands);  in parseOptionalOpr()
7406       res = parseSDWASel(Operands, Op.Name, Op.Type);  in parseOptionalOpr()
7408       res = parseSDWADstUnused(Operands);  in parseOptionalOpr()
7413       res = parseOperandArrayWithPrefix(Op.Name, Operands, Op.Type,  in parseOptionalOpr()
7416       res = parseDim(Operands);  in parseOptionalOpr()
7418       res = parseCPol(Operands);  in parseOptionalOpr()
7420       res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);  in parseOptionalOpr()
7429 OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) {  in parseOModOperand()  argument
7432     return parseIntWithPrefix("mul", Operands,  in parseOModOperand()
7437     return parseIntWithPrefix("div", Operands,  in parseOModOperand()
7444 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands) {  in cvtVOP3OpSel()  argument
7445   cvtVOP3P(Inst, Operands);  in cvtVOP3OpSel()
7479 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)  in cvtVOP3Interp()  argument
7487     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtVOP3Interp()
7490   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtVOP3Interp()
7491     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtVOP3Interp()
7506     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);  in cvtVOP3Interp()
7510     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);  in cvtVOP3Interp()
7514     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);  in cvtVOP3Interp()
7518 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,  in cvtVOP3()  argument
7525     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtVOP3()
7530     for (unsigned E = Operands.size(); I != E; ++I) {  in cvtVOP3()
7531       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtVOP3()
7544     for (unsigned E = Operands.size(); I != E; ++I) {  in cvtVOP3()
7545       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtVOP3()
7555     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);  in cvtVOP3()
7559     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);  in cvtVOP3()
7586 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {  in cvtVOP3()  argument
7588   cvtVOP3(Inst, Operands, OptionalIdx);  in cvtVOP3()
7591 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,  in cvtVOP3P()  argument
7608     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);  in cvtVOP3P()
7614     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,  in cvtVOP3P()
7620     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);  in cvtVOP3P()
7621     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);  in cvtVOP3P()
7673 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {  in cvtVOP3P()  argument
7675   cvtVOP3(Inst, Operands, OptIdx);  in cvtVOP3P()
7676   cvtVOP3P(Inst, Operands, OptIdx);  in cvtVOP3P()
7768 OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) {  in parseDim()  argument
7784   Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,  in parseDim()
7793 OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {  in parseDPP8()  argument
7826   Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));  in parseDPP8()
7832                                     const OperandVector &Operands) {  in isSupportedDPPCtrl()  argument
7934 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {  in parseDPPCtrl()  argument
7938       !isSupportedDPPCtrl(getTokenStr(), Operands))  in parseDPPCtrl()
7964   Operands.push_back(  in parseDPPCtrl()
7989 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {  in cvtDPP()  argument
7998     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtDPP()
8002   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtDPP()
8010     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtDPP()
8052     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);  in cvtDPP()
8053     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);  in cvtDPP()
8054     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);  in cvtDPP()
8056       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);  in cvtDPP()
8066 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,  in parseSDWASel()  argument
8096   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));  in parseSDWASel()
8101 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {  in parseSDWADstUnused()  argument
8126   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySdwaDstUnused));  in parseSDWADstUnused()
8130 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP1()  argument
8131   cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);  in cvtSdwaVOP1()
8134 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP2()  argument
8135   cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);  in cvtSdwaVOP2()
8138 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP2b()  argument
8139   cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);  in cvtSdwaVOP2b()
8142 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP2e()  argument
8143   cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);  in cvtSdwaVOP2e()
8146 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOPC()  argument
8147   cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());  in cvtSdwaVOPC()
8150 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,  in cvtSDWA()  argument
8163     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtSDWA()
8166   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtSDWA()
8167     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtSDWA()
8203       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);  in cvtSDWA()
8205         addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);  in cvtSDWA()
8207 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);  in cvtSDWA()
8208 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::U…  in cvtSDWA()
8209 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD…  in cvtSDWA()
8213       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);  in cvtSDWA()
8215         addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);  in cvtSDWA()
8217 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);  in cvtSDWA()
8218 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::U…  in cvtSDWA()
8219 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD…  in cvtSDWA()
8220 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD…  in cvtSDWA()
8225         addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);  in cvtSDWA()
8226 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD…  in cvtSDWA()
8227 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD…  in cvtSDWA()
8333 OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) {  in parseEndpgmOp()  argument
8347   Operands.push_back(  in parseEndpgmOp()