Lines Matching refs:AMDGPU
39 using namespace llvm::AMDGPU;
254 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrImmWithInt16InputMods()
258 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrImmWithInt32InputMods()
262 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); in isRegOrImmWithInt64InputMods()
266 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrImmWithFP16InputMods()
270 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrImmWithFP32InputMods()
274 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); in isRegOrImmWithFP64InputMods()
278 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVReg()
279 isRegClass(AMDGPU::VReg_64RegClassID) || in isVReg()
280 isRegClass(AMDGPU::VReg_96RegClassID) || in isVReg()
281 isRegClass(AMDGPU::VReg_128RegClassID) || in isVReg()
282 isRegClass(AMDGPU::VReg_160RegClassID) || in isVReg()
283 isRegClass(AMDGPU::VReg_192RegClassID) || in isVReg()
284 isRegClass(AMDGPU::VReg_256RegClassID) || in isVReg()
285 isRegClass(AMDGPU::VReg_512RegClassID) || in isVReg()
286 isRegClass(AMDGPU::VReg_1024RegClassID); in isVReg()
290 return isRegClass(AMDGPU::VGPR_32RegClassID); in isVReg32()
298 return isRegKind() && getReg() == AMDGPU::SGPR_NULL; in isNull()
379 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16); in isSCSrcB16()
387 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32); in isSCSrcB32()
391 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); in isSCSrcB64()
397 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); in isSCSrcF16()
405 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32); in isSCSrcF32()
409 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64); in isSCSrcF64()
469 return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) || in isSSrcOrLdsB32()
474 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32); in isVCSrcB32()
478 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); in isVCSrcB64()
482 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16); in isVCSrcB16()
490 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32); in isVCSrcF32()
494 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64); in isVCSrcF64()
498 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); in isVCSrcF16()
554 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32); in isVISrcB32()
558 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16); in isVISrcB16()
566 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32); in isVISrcF32()
570 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16); in isVISrcF16()
578 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64); in isVISrc_64B64()
582 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64); in isVISrc_64F64()
586 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32); in isVISrc_64V2FP32()
590 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32); in isVISrc_64V2INT32()
594 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64); in isVISrc_256B64()
598 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64); in isVISrc_256F64()
602 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16); in isVISrc_128B16()
610 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32); in isVISrc_128B32()
614 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32); in isVISrc_128F32()
618 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32); in isVISrc_256V2FP32()
622 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32); in isVISrc_256V2INT32()
626 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32); in isVISrc_512B32()
630 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16); in isVISrc_512B16()
638 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32); in isVISrc_512F32()
642 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16); in isVISrc_512F16()
650 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32); in isVISrc_1024B32()
654 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16); in isVISrc_1024B16()
662 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32); in isVISrc_1024F32()
666 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16); in isVISrc_1024F16()
674 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32); in isAISrcB32()
678 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16); in isAISrcB16()
686 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32); in isAISrcF32()
690 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16); in isAISrcF16()
698 return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64); in isAISrc_64B64()
702 return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64); in isAISrc_64F64()
706 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32); in isAISrc_128B32()
710 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16); in isAISrc_128B16()
718 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32); in isAISrc_128F32()
722 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16); in isAISrc_128F16()
730 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16); in isVISrc_128F16()
738 return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64); in isAISrc_256B64()
742 return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64); in isAISrc_256F64()
746 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32); in isAISrc_512B32()
750 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16); in isAISrc_512B16()
758 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32); in isAISrc_512F32()
762 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16); in isAISrc_512F16()
770 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32); in isAISrc_1024B32()
774 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16); in isAISrc_1024B16()
782 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32); in isAISrc_1024F32()
786 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16); in isAISrc_1024F16()
1293 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in AMDGPUAsmParser()
1321 return AMDGPU::hasMIMG_R128(getSTI()); in hasMIMG_R128()
1325 return AMDGPU::hasPackedD16(getSTI()); in hasPackedD16()
1329 return AMDGPU::hasGFX10A16(getSTI()); in hasGFX10A16()
1332 bool hasG16() const { return AMDGPU::hasG16(getSTI()); } in hasG16()
1335 return AMDGPU::isSI(getSTI()); in isSI()
1339 return AMDGPU::isCI(getSTI()); in isCI()
1343 return AMDGPU::isVI(getSTI()); in isVI()
1347 return AMDGPU::isGFX9(getSTI()); in isGFX9()
1351 return AMDGPU::isGFX90A(getSTI()); in isGFX90A()
1355 return AMDGPU::isGFX9Plus(getSTI()); in isGFX9Plus()
1359 return AMDGPU::isGFX10(getSTI()); in isGFX10()
1362 bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); } in isGFX10Plus()
1365 return AMDGPU::isGFX10_BEncoding(getSTI()); in isGFX10_BEncoding()
1369 return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]; in hasInv2PiInlineImm()
1373 return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets]; in hasFlatOffsets()
1377 return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; in hasArchitectedFlatScratch()
1387 return getFeatureBits()[AMDGPU::FeatureIntClamp]; in hasIntClamp()
1716 case AMDGPU::OPERAND_REG_IMM_INT32: in getOpFltSemantics()
1717 case AMDGPU::OPERAND_REG_IMM_FP32: in getOpFltSemantics()
1718 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in getOpFltSemantics()
1719 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getOpFltSemantics()
1720 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in getOpFltSemantics()
1721 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in getOpFltSemantics()
1722 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in getOpFltSemantics()
1723 case AMDGPU::OPERAND_REG_IMM_V2FP32: in getOpFltSemantics()
1724 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in getOpFltSemantics()
1725 case AMDGPU::OPERAND_REG_IMM_V2INT32: in getOpFltSemantics()
1727 case AMDGPU::OPERAND_REG_IMM_INT64: in getOpFltSemantics()
1728 case AMDGPU::OPERAND_REG_IMM_FP64: in getOpFltSemantics()
1729 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in getOpFltSemantics()
1730 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in getOpFltSemantics()
1731 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in getOpFltSemantics()
1733 case AMDGPU::OPERAND_REG_IMM_INT16: in getOpFltSemantics()
1734 case AMDGPU::OPERAND_REG_IMM_FP16: in getOpFltSemantics()
1735 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in getOpFltSemantics()
1736 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in getOpFltSemantics()
1737 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in getOpFltSemantics()
1738 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in getOpFltSemantics()
1739 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in getOpFltSemantics()
1740 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in getOpFltSemantics()
1741 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in getOpFltSemantics()
1742 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in getOpFltSemantics()
1743 case AMDGPU::OPERAND_REG_IMM_V2INT16: in getOpFltSemantics()
1744 case AMDGPU::OPERAND_REG_IMM_V2FP16: in getOpFltSemantics()
1784 return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi); in isInlineableLiteralOp16()
1809 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1824 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1831 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1845 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1903 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVRegWithInputMods()
1905 (isRegClass(AMDGPU::VReg_64RegClassID) && in isVRegWithInputMods()
1906 AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]); in isVRegWithInputMods()
1913 return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type); in isSDWAOperand()
1936 return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || in isBoolReg()
1937 (FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32())); in isBoolReg()
1958 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), in addImmOperands()
1974 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1977 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1987 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
1988 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
1989 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
1990 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
1991 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in addLiteralImmOperand()
1992 if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), in addLiteralImmOperand()
2000 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
2018 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
2019 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
2020 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
2021 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
2022 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
2023 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
2024 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
2025 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
2026 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
2027 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
2028 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
2029 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
2030 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
2031 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
2032 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
2033 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in addLiteralImmOperand()
2034 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
2035 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
2036 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in addLiteralImmOperand()
2037 case AMDGPU::OPERAND_REG_IMM_V2FP32: in addLiteralImmOperand()
2038 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in addLiteralImmOperand()
2039 case AMDGPU::OPERAND_REG_IMM_V2INT32: { in addLiteralImmOperand()
2063 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
2064 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
2065 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
2066 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
2067 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
2068 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
2069 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
2070 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
2071 case AMDGPU::OPERAND_REG_IMM_V2FP32: in addLiteralImmOperand()
2072 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in addLiteralImmOperand()
2073 case AMDGPU::OPERAND_REG_IMM_V2INT32: in addLiteralImmOperand()
2074 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in addLiteralImmOperand()
2076 AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), in addLiteralImmOperand()
2087 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
2088 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
2089 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
2090 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
2091 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in addLiteralImmOperand()
2092 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2102 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
2103 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
2104 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
2105 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
2106 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
2107 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
2109 AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
2120 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
2121 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
2122 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
2123 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { in addLiteralImmOperand()
2125 assert(AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
2155 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); in addRegOperands()
2160 case AMDGPU::SRC_SHARED_BASE: in isInlineValue()
2161 case AMDGPU::SRC_SHARED_LIMIT: in isInlineValue()
2162 case AMDGPU::SRC_PRIVATE_BASE: in isInlineValue()
2163 case AMDGPU::SRC_PRIVATE_LIMIT: in isInlineValue()
2164 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in isInlineValue()
2166 case AMDGPU::SRC_VCCZ: in isInlineValue()
2167 case AMDGPU::SRC_EXECZ: in isInlineValue()
2168 case AMDGPU::SRC_SCC: in isInlineValue()
2170 case AMDGPU::SGPR_NULL: in isInlineValue()
2189 case 1: return AMDGPU::VGPR_32RegClassID; in getRegClass()
2190 case 2: return AMDGPU::VReg_64RegClassID; in getRegClass()
2191 case 3: return AMDGPU::VReg_96RegClassID; in getRegClass()
2192 case 4: return AMDGPU::VReg_128RegClassID; in getRegClass()
2193 case 5: return AMDGPU::VReg_160RegClassID; in getRegClass()
2194 case 6: return AMDGPU::VReg_192RegClassID; in getRegClass()
2195 case 7: return AMDGPU::VReg_224RegClassID; in getRegClass()
2196 case 8: return AMDGPU::VReg_256RegClassID; in getRegClass()
2197 case 16: return AMDGPU::VReg_512RegClassID; in getRegClass()
2198 case 32: return AMDGPU::VReg_1024RegClassID; in getRegClass()
2203 case 1: return AMDGPU::TTMP_32RegClassID; in getRegClass()
2204 case 2: return AMDGPU::TTMP_64RegClassID; in getRegClass()
2205 case 4: return AMDGPU::TTMP_128RegClassID; in getRegClass()
2206 case 8: return AMDGPU::TTMP_256RegClassID; in getRegClass()
2207 case 16: return AMDGPU::TTMP_512RegClassID; in getRegClass()
2212 case 1: return AMDGPU::SGPR_32RegClassID; in getRegClass()
2213 case 2: return AMDGPU::SGPR_64RegClassID; in getRegClass()
2214 case 3: return AMDGPU::SGPR_96RegClassID; in getRegClass()
2215 case 4: return AMDGPU::SGPR_128RegClassID; in getRegClass()
2216 case 5: return AMDGPU::SGPR_160RegClassID; in getRegClass()
2217 case 6: return AMDGPU::SGPR_192RegClassID; in getRegClass()
2218 case 7: return AMDGPU::SGPR_224RegClassID; in getRegClass()
2219 case 8: return AMDGPU::SGPR_256RegClassID; in getRegClass()
2220 case 16: return AMDGPU::SGPR_512RegClassID; in getRegClass()
2225 case 1: return AMDGPU::AGPR_32RegClassID; in getRegClass()
2226 case 2: return AMDGPU::AReg_64RegClassID; in getRegClass()
2227 case 3: return AMDGPU::AReg_96RegClassID; in getRegClass()
2228 case 4: return AMDGPU::AReg_128RegClassID; in getRegClass()
2229 case 5: return AMDGPU::AReg_160RegClassID; in getRegClass()
2230 case 6: return AMDGPU::AReg_192RegClassID; in getRegClass()
2231 case 7: return AMDGPU::AReg_224RegClassID; in getRegClass()
2232 case 8: return AMDGPU::AReg_256RegClassID; in getRegClass()
2233 case 16: return AMDGPU::AReg_512RegClassID; in getRegClass()
2234 case 32: return AMDGPU::AReg_1024RegClassID; in getRegClass()
2242 .Case("exec", AMDGPU::EXEC) in getSpecialRegForName()
2243 .Case("vcc", AMDGPU::VCC) in getSpecialRegForName()
2244 .Case("flat_scratch", AMDGPU::FLAT_SCR) in getSpecialRegForName()
2245 .Case("xnack_mask", AMDGPU::XNACK_MASK) in getSpecialRegForName()
2246 .Case("shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2247 .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2248 .Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2249 .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2250 .Case("private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2251 .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2252 .Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2253 .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2254 .Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2255 .Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2256 .Case("lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2257 .Case("src_lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2258 .Case("m0", AMDGPU::M0) in getSpecialRegForName()
2259 .Case("vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2260 .Case("src_vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2261 .Case("execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2262 .Case("src_execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2263 .Case("scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2264 .Case("src_scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2265 .Case("tba", AMDGPU::TBA) in getSpecialRegForName()
2266 .Case("tma", AMDGPU::TMA) in getSpecialRegForName()
2267 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) in getSpecialRegForName()
2268 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) in getSpecialRegForName()
2269 .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO) in getSpecialRegForName()
2270 .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI) in getSpecialRegForName()
2271 .Case("vcc_lo", AMDGPU::VCC_LO) in getSpecialRegForName()
2272 .Case("vcc_hi", AMDGPU::VCC_HI) in getSpecialRegForName()
2273 .Case("exec_lo", AMDGPU::EXEC_LO) in getSpecialRegForName()
2274 .Case("exec_hi", AMDGPU::EXEC_HI) in getSpecialRegForName()
2275 .Case("tma_lo", AMDGPU::TMA_LO) in getSpecialRegForName()
2276 .Case("tma_hi", AMDGPU::TMA_HI) in getSpecialRegForName()
2277 .Case("tba_lo", AMDGPU::TBA_LO) in getSpecialRegForName()
2278 .Case("tba_hi", AMDGPU::TBA_HI) in getSpecialRegForName()
2279 .Case("pc", AMDGPU::PC_REG) in getSpecialRegForName()
2280 .Case("null", AMDGPU::SGPR_NULL) in getSpecialRegForName()
2281 .Default(AMDGPU::NoRegister); in getSpecialRegForName()
2319 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2320 Reg = AMDGPU::EXEC; in AddNextRegisterToList()
2324 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
2325 Reg = AMDGPU::FLAT_SCR; in AddNextRegisterToList()
2329 if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) { in AddNextRegisterToList()
2330 Reg = AMDGPU::XNACK_MASK; in AddNextRegisterToList()
2334 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2335 Reg = AMDGPU::VCC; in AddNextRegisterToList()
2339 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2340 Reg = AMDGPU::TBA; in AddNextRegisterToList()
2344 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
2345 Reg = AMDGPU::TMA; in AddNextRegisterToList()
2427 return getSpecialRegForName(Str) != AMDGPU::NoRegister; in isRegister()
2453 return AMDGPU::NoRegister; in getRegularReg()
2460 return AMDGPU::NoRegister; in getRegularReg()
2467 return AMDGPU::NoRegister; in getRegularReg()
2541 return AMDGPU::NoRegister; in ParseRegularReg()
2553 return AMDGPU::NoRegister; in ParseRegularReg()
2559 return AMDGPU::NoRegister; in ParseRegularReg()
2568 unsigned Reg = AMDGPU::NoRegister; in ParseRegList()
2573 return AMDGPU::NoRegister; in ParseRegList()
2580 return AMDGPU::NoRegister; in ParseRegList()
2583 return AMDGPU::NoRegister; in ParseRegList()
2594 return AMDGPU::NoRegister; in ParseRegList()
2598 return AMDGPU::NoRegister; in ParseRegList()
2602 return AMDGPU::NoRegister; in ParseRegList()
2605 return AMDGPU::NoRegister; in ParseRegList()
2610 return AMDGPU::NoRegister; in ParseRegList()
2623 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2627 if (Reg == AMDGPU::NoRegister) in ParseAMDGPURegister()
2634 if (Reg == AMDGPU::NoRegister) { in ParseAMDGPURegister()
2640 if (Reg == AMDGPU::SGPR_NULL) { in ParseAMDGPURegister()
2654 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2691 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6) in updateGprCountSymbols()
3071 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in checkTargetMatchPredicate()
3072 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in checkTargetMatchPredicate()
3075 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
3077 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
3142 case AMDGPU::FLAT_SCR: in findImplicitSGPRReadInVOP()
3143 case AMDGPU::VCC: in findImplicitSGPRReadInVOP()
3144 case AMDGPU::VCC_LO: in findImplicitSGPRReadInVOP()
3145 case AMDGPU::VCC_HI: in findImplicitSGPRReadInVOP()
3146 case AMDGPU::M0: in findImplicitSGPRReadInVOP()
3152 return AMDGPU::NoRegister; in findImplicitSGPRReadInVOP()
3163 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) { in isInlineConstant()
3170 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant()
3174 return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm()); in isInlineConstant()
3176 return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm()); in isInlineConstant()
3179 if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 || in isInlineConstant()
3180 OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 || in isInlineConstant()
3181 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16) in isInlineConstant()
3182 return AMDGPU::isInlinableIntLiteral(Val); in isInlineConstant()
3184 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 || in isInlineConstant()
3185 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 || in isInlineConstant()
3186 OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16) in isInlineConstant()
3187 return AMDGPU::isInlinableIntLiteralV216(Val); in isInlineConstant()
3189 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 || in isInlineConstant()
3190 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 || in isInlineConstant()
3191 OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16) in isInlineConstant()
3192 return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm()); in isInlineConstant()
3194 return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm()); in isInlineConstant()
3207 case AMDGPU::V_LSHLREV_B64_e64: in getConstantBusLimit()
3208 case AMDGPU::V_LSHLREV_B64_gfx10: in getConstantBusLimit()
3209 case AMDGPU::V_LSHRREV_B64_e64: in getConstantBusLimit()
3210 case AMDGPU::V_LSHRREV_B64_gfx10: in getConstantBusLimit()
3211 case AMDGPU::V_ASHRREV_I64_e64: in getConstantBusLimit()
3212 case AMDGPU::V_ASHRREV_I64_gfx10: in getConstantBusLimit()
3213 case AMDGPU::V_LSHL_B64_e64: in getConstantBusLimit()
3214 case AMDGPU::V_LSHR_B64_e64: in getConstantBusLimit()
3215 case AMDGPU::V_ASHR_I64_e64: in getConstantBusLimit()
3241 unsigned LastSGPR = AMDGPU::NoRegister; in validateConstantBusLimitations()
3252 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) { in validateConstantBusLimitations()
3258 if (SGPRUsed != AMDGPU::NoRegister) { in validateConstantBusLimitations()
3263 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateConstantBusLimitations()
3264 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateConstantBusLimitations()
3265 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateConstantBusLimitations()
3300 unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx); in validateConstantBusLimitations()
3331 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in validateEarlyClobberLimitations()
3339 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateEarlyClobberLimitations()
3340 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateEarlyClobberLimitations()
3341 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateEarlyClobberLimitations()
3372 int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp); in validateIntClampSupported()
3388 int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); in validateMIMGDataSize()
3389 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGDataSize()
3390 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()
3397 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); in validateMIMGDataSize()
3406 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGDataSize()
3421 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3423 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGAddrSize()
3424 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGAddrSize()
3425 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize()
3426 int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in validateMIMGAddrSize()
3427 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGAddrSize()
3428 int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16); in validateMIMGAddrSize()
3438 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGAddrSize()
3442 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()
3446 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16()); in validateMIMGAddrSize()
3472 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGAtomicDMask()
3490 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGGatherDMask()
3508 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGMSAA()
3509 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGMSAA()
3510 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGMSAA()
3515 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGMSAA()
3519 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGMSAA()
3527 case AMDGPU::V_MOVRELS_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3528 case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3529 case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3548 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMovrels()
3572 if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi) in validateMAIAccWrite()
3575 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMAIAccWrite()
3608 for (auto Name : {AMDGPU::OpName::src0_modifiers, in validateDivScale()
3609 AMDGPU::OpName::src2_modifiers, in validateDivScale()
3610 AMDGPU::OpName::src2_modifiers}) { in validateDivScale()
3611 if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name)) in validateDivScale()
3629 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGD16()
3645 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGDim()
3659 case AMDGPU::V_SUBREV_F32_e32: in IsRevOpcode()
3660 case AMDGPU::V_SUBREV_F32_e64: in IsRevOpcode()
3661 case AMDGPU::V_SUBREV_F32_e32_gfx10: in IsRevOpcode()
3662 case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7: in IsRevOpcode()
3663 case AMDGPU::V_SUBREV_F32_e32_vi: in IsRevOpcode()
3664 case AMDGPU::V_SUBREV_F32_e64_gfx10: in IsRevOpcode()
3665 case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7: in IsRevOpcode()
3666 case AMDGPU::V_SUBREV_F32_e64_vi: in IsRevOpcode()
3668 case AMDGPU::V_SUBREV_CO_U32_e32: in IsRevOpcode()
3669 case AMDGPU::V_SUBREV_CO_U32_e64: in IsRevOpcode()
3670 case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
3671 case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
3673 case AMDGPU::V_SUBBREV_U32_e32: in IsRevOpcode()
3674 case AMDGPU::V_SUBBREV_U32_e64: in IsRevOpcode()
3675 case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7: in IsRevOpcode()
3676 case AMDGPU::V_SUBBREV_U32_e32_vi: in IsRevOpcode()
3677 case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7: in IsRevOpcode()
3678 case AMDGPU::V_SUBBREV_U32_e64_vi: in IsRevOpcode()
3680 case AMDGPU::V_SUBREV_U32_e32: in IsRevOpcode()
3681 case AMDGPU::V_SUBREV_U32_e64: in IsRevOpcode()
3682 case AMDGPU::V_SUBREV_U32_e32_gfx9: in IsRevOpcode()
3683 case AMDGPU::V_SUBREV_U32_e32_vi: in IsRevOpcode()
3684 case AMDGPU::V_SUBREV_U32_e64_gfx9: in IsRevOpcode()
3685 case AMDGPU::V_SUBREV_U32_e64_vi: in IsRevOpcode()
3687 case AMDGPU::V_SUBREV_F16_e32: in IsRevOpcode()
3688 case AMDGPU::V_SUBREV_F16_e64: in IsRevOpcode()
3689 case AMDGPU::V_SUBREV_F16_e32_gfx10: in IsRevOpcode()
3690 case AMDGPU::V_SUBREV_F16_e32_vi: in IsRevOpcode()
3691 case AMDGPU::V_SUBREV_F16_e64_gfx10: in IsRevOpcode()
3692 case AMDGPU::V_SUBREV_F16_e64_vi: in IsRevOpcode()
3694 case AMDGPU::V_SUBREV_U16_e32: in IsRevOpcode()
3695 case AMDGPU::V_SUBREV_U16_e64: in IsRevOpcode()
3696 case AMDGPU::V_SUBREV_U16_e32_vi: in IsRevOpcode()
3697 case AMDGPU::V_SUBREV_U16_e64_vi: in IsRevOpcode()
3699 case AMDGPU::V_SUBREV_CO_U32_e32_gfx9: in IsRevOpcode()
3700 case AMDGPU::V_SUBREV_CO_U32_e64_gfx10: in IsRevOpcode()
3701 case AMDGPU::V_SUBREV_CO_U32_e64_gfx9: in IsRevOpcode()
3703 case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9: in IsRevOpcode()
3704 case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9: in IsRevOpcode()
3706 case AMDGPU::V_SUBREV_NC_U32_e32_gfx10: in IsRevOpcode()
3707 case AMDGPU::V_SUBREV_NC_U32_e64_gfx10: in IsRevOpcode()
3709 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in IsRevOpcode()
3710 case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10: in IsRevOpcode()
3712 case AMDGPU::V_LSHRREV_B32_e32: in IsRevOpcode()
3713 case AMDGPU::V_LSHRREV_B32_e64: in IsRevOpcode()
3714 case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
3715 case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
3716 case AMDGPU::V_LSHRREV_B32_e32_vi: in IsRevOpcode()
3717 case AMDGPU::V_LSHRREV_B32_e64_vi: in IsRevOpcode()
3718 case AMDGPU::V_LSHRREV_B32_e32_gfx10: in IsRevOpcode()
3719 case AMDGPU::V_LSHRREV_B32_e64_gfx10: in IsRevOpcode()
3721 case AMDGPU::V_ASHRREV_I32_e32: in IsRevOpcode()
3722 case AMDGPU::V_ASHRREV_I32_e64: in IsRevOpcode()
3723 case AMDGPU::V_ASHRREV_I32_e32_gfx10: in IsRevOpcode()
3724 case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
3725 case AMDGPU::V_ASHRREV_I32_e32_vi: in IsRevOpcode()
3726 case AMDGPU::V_ASHRREV_I32_e64_gfx10: in IsRevOpcode()
3727 case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
3728 case AMDGPU::V_ASHRREV_I32_e64_vi: in IsRevOpcode()
3730 case AMDGPU::V_LSHLREV_B32_e32: in IsRevOpcode()
3731 case AMDGPU::V_LSHLREV_B32_e64: in IsRevOpcode()
3732 case AMDGPU::V_LSHLREV_B32_e32_gfx10: in IsRevOpcode()
3733 case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
3734 case AMDGPU::V_LSHLREV_B32_e32_vi: in IsRevOpcode()
3735 case AMDGPU::V_LSHLREV_B32_e64_gfx10: in IsRevOpcode()
3736 case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
3737 case AMDGPU::V_LSHLREV_B32_e64_vi: in IsRevOpcode()
3739 case AMDGPU::V_LSHLREV_B16_e32: in IsRevOpcode()
3740 case AMDGPU::V_LSHLREV_B16_e64: in IsRevOpcode()
3741 case AMDGPU::V_LSHLREV_B16_e32_vi: in IsRevOpcode()
3742 case AMDGPU::V_LSHLREV_B16_e64_vi: in IsRevOpcode()
3743 case AMDGPU::V_LSHLREV_B16_gfx10: in IsRevOpcode()
3745 case AMDGPU::V_LSHRREV_B16_e32: in IsRevOpcode()
3746 case AMDGPU::V_LSHRREV_B16_e64: in IsRevOpcode()
3747 case AMDGPU::V_LSHRREV_B16_e32_vi: in IsRevOpcode()
3748 case AMDGPU::V_LSHRREV_B16_e64_vi: in IsRevOpcode()
3749 case AMDGPU::V_LSHRREV_B16_gfx10: in IsRevOpcode()
3751 case AMDGPU::V_ASHRREV_I16_e32: in IsRevOpcode()
3752 case AMDGPU::V_ASHRREV_I16_e64: in IsRevOpcode()
3753 case AMDGPU::V_ASHRREV_I16_e32_vi: in IsRevOpcode()
3754 case AMDGPU::V_ASHRREV_I16_e64_vi: in IsRevOpcode()
3755 case AMDGPU::V_ASHRREV_I16_gfx10: in IsRevOpcode()
3757 case AMDGPU::V_LSHLREV_B64_e64: in IsRevOpcode()
3758 case AMDGPU::V_LSHLREV_B64_gfx10: in IsRevOpcode()
3759 case AMDGPU::V_LSHLREV_B64_vi: in IsRevOpcode()
3761 case AMDGPU::V_LSHRREV_B64_e64: in IsRevOpcode()
3762 case AMDGPU::V_LSHRREV_B64_gfx10: in IsRevOpcode()
3763 case AMDGPU::V_LSHRREV_B64_vi: in IsRevOpcode()
3765 case AMDGPU::V_ASHRREV_I64_e64: in IsRevOpcode()
3766 case AMDGPU::V_ASHRREV_I64_gfx10: in IsRevOpcode()
3767 case AMDGPU::V_ASHRREV_I64_vi: in IsRevOpcode()
3769 case AMDGPU::V_PK_LSHLREV_B16: in IsRevOpcode()
3770 case AMDGPU::V_PK_LSHLREV_B16_gfx10: in IsRevOpcode()
3771 case AMDGPU::V_PK_LSHLREV_B16_vi: in IsRevOpcode()
3773 case AMDGPU::V_PK_LSHRREV_B16: in IsRevOpcode()
3774 case AMDGPU::V_PK_LSHRREV_B16_gfx10: in IsRevOpcode()
3775 case AMDGPU::V_PK_LSHRREV_B16_vi: in IsRevOpcode()
3776 case AMDGPU::V_PK_ASHRREV_I16: in IsRevOpcode()
3777 case AMDGPU::V_PK_ASHRREV_I16_gfx10: in IsRevOpcode()
3778 case AMDGPU::V_PK_ASHRREV_I16_vi: in IsRevOpcode()
3834 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateFlatOffset()
3847 unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), true); in validateFlatOffset()
3854 unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), false); in validateFlatOffset()
3885 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateSMEMOffset()
3894 bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode); in validateSMEMOffset()
3895 if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) || in validateSMEMOffset()
3896 AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer)) in validateSMEMOffset()
3912 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateSOPLiteral()
3913 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateSOPLiteral()
3926 if (AMDGPU::isSISrcOperand(Desc, OpIdx)) { in validateSOPLiteral()
3944 if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 || in validateOpSel()
3945 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) { in validateOpSel()
3946 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
3958 int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl); in validateDPP()
3963 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) { in validateDPP()
3965 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateDPP()
3967 getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) { in validateDPP()
3980 return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) || in validateVccOperand()
3981 (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO); in validateVccOperand()
3992 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateVOP3Literal()
3993 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateVOP3Literal()
3994 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateVOP3Literal()
4008 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) in validateVOP3Literal()
4012 getFeatureBits()[AMDGPU::FeatureMFMAInlineLiteralBug]) { in validateVOP3Literal()
4033 if (!getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { in validateVOP3Literal()
4049 int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx); in IsAGPROperand()
4057 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
4059 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()
4070 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in validateAGPRLdSt()
4071 : AMDGPU::OpName::vdata; in validateAGPRLdSt()
4074 int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI); in validateAGPRLdSt()
4078 int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI); in validateAGPRLdSt()
4084 if (FB[AMDGPU::FeatureGFX90AInsts]) { in validateAGPRLdSt()
4095 if (!FB[AMDGPU::FeatureGFX90AInsts]) in validateVGPRAlign()
4099 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()
4100 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
4106 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in validateVGPRAlign()
4110 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4112 if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1)) in validateVGPRAlign()
4123 if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) in validateGWS()
4127 if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi && in validateGWS()
4128 Opc != AMDGPU::DS_GWS_SEMA_BR_vi) in validateGWS()
4132 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
4134 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0); in validateGWS()
4137 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()
4150 int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in validateCoherencyBits()
4151 AMDGPU::OpName::cpol); in validateCoherencyBits()
4159 (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) { in validateCoherencyBits()
4279 Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts] in validateInstruction()
4871 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in ParseDirectiveHSACodeObjectISA()
4924 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
4927 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
4936 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
4939 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
4967 AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI()); in ParseDirectiveAMDKernelCodeT()
5093 if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin, in ParseDirectivePALMetadataBegin()
5094 AMDGPU::PALMD::AssemblerDirectiveEnd, String)) in ParseDirectivePALMetadataBegin()
5149 unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI()); in ParseDirectiveAMDGPULDS()
5195 if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) in ParseDirective()
5213 if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) in ParseDirective()
5235 for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true); in subtargetHasRegister()
5242 for (MCRegAliasIterator R(AMDGPU::SGPR104_SGPR105, &MRI, true); in subtargetHasRegister()
5249 case AMDGPU::SRC_SHARED_BASE: in subtargetHasRegister()
5250 case AMDGPU::SRC_SHARED_LIMIT: in subtargetHasRegister()
5251 case AMDGPU::SRC_PRIVATE_BASE: in subtargetHasRegister()
5252 case AMDGPU::SRC_PRIVATE_LIMIT: in subtargetHasRegister()
5253 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in subtargetHasRegister()
5255 case AMDGPU::TBA: in subtargetHasRegister()
5256 case AMDGPU::TBA_LO: in subtargetHasRegister()
5257 case AMDGPU::TBA_HI: in subtargetHasRegister()
5258 case AMDGPU::TMA: in subtargetHasRegister()
5259 case AMDGPU::TMA_LO: in subtargetHasRegister()
5260 case AMDGPU::TMA_HI: in subtargetHasRegister()
5262 case AMDGPU::XNACK_MASK: in subtargetHasRegister()
5263 case AMDGPU::XNACK_MASK_LO: in subtargetHasRegister()
5264 case AMDGPU::XNACK_MASK_HI: in subtargetHasRegister()
5266 case AMDGPU::SGPR_NULL: in subtargetHasRegister()
5280 case AMDGPU::FLAT_SCR: in subtargetHasRegister()
5281 case AMDGPU::FLAT_SCR_LO: in subtargetHasRegister()
5282 case AMDGPU::FLAT_SCR_HI: in subtargetHasRegister()
5291 for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true); in subtargetHasRegister()
5526 CPolOn = AMDGPU::CPol::GLC; in parseCPol()
5528 CPolOff = AMDGPU::CPol::GLC; in parseCPol()
5530 CPolOn = AMDGPU::CPol::SLC; in parseCPol()
5532 CPolOff = AMDGPU::CPol::SLC; in parseCPol()
5534 CPolOn = AMDGPU::CPol::DLC; in parseCPol()
5536 CPolOff = AMDGPU::CPol::DLC; in parseCPol()
5538 CPolOn = AMDGPU::CPol::SCC; in parseCPol()
5540 CPolOff = AMDGPU::CPol::SCC; in parseCPol()
5544 if (!isGFX10Plus() && ((CPolOn | CPolOff) & AMDGPU::CPol::DLC)) { in parseCPol()
5549 if (!isGFX90A() && ((CPolOn | CPolOff) & AMDGPU::CPol::SCC)) { in parseCPol()
5630 using namespace llvm::AMDGPU::MTBUFFormat; in parseDfmtNfmt()
5663 using namespace llvm::AMDGPU::MTBUFFormat; in parseUfmt()
5681 using namespace llvm::AMDGPU::MTBUFFormat; in matchDfmtNfmt()
5704 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicSplitFormat()
5748 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicUnifiedFormat()
5765 using namespace llvm::AMDGPU::MTBUFFormat; in parseNumericFormat()
5780 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicOrNumericFormat()
5808 using namespace llvm::AMDGPU::MTBUFFormat; in parseFORMAT()
5885 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSOffset01()
5911 (Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx10 || in cvtDSImpl()
5912 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7 || in cvtDSImpl()
5913 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle : in cvtDSImpl()
5921 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSImpl()
5946 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister)); in cvtExp()
5969 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
5970 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
5974 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
5991 const AMDGPU::IsaVersion ISA, in encodeCnt()
6025 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
6061 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCntOps()
6092 using namespace llvm::AMDGPU::Hwreg; in parseHwregBody()
6128 using namespace llvm::AMDGPU::Hwreg; in validateHwreg()
6154 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()
6194 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgBody()
6229 using namespace llvm::AMDGPU::SendMsg; in validateSendMsg()
6265 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgOp()
6375 using namespace llvm::AMDGPU::Exp; in parseExpTgt()
6617 using namespace llvm::AMDGPU::Swizzle; in encodeBitmaskPerm()
6662 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleQuadPerm()
6678 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBroadcast()
6706 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleReverse()
6728 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleSwap()
6750 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBitmaskPerm()
6812 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleMacro()
6876 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMacro()
6921 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMode()
7011 IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; in cvtMubufImpl()
7016 int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode()); in cvtMubufImpl()
7066 int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode()); in cvtMubufImpl()
7162 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::tfe) != -1) in cvtMIMG()
7182 IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; in cvtSMEMAtomic()
7187 int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode()); in cvtSMEMAtomic()
7224 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset)) in cvtSMEMAtomic()
7450 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3OpSel()
7451 AMDGPU::OpName::src1, in cvtVOP3OpSel()
7452 AMDGPU::OpName::src2 }; in cvtVOP3OpSel()
7454 SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1; in cvtVOP3OpSel()
7458 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3OpSel()
7462 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in cvtVOP3OpSel()
7470 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS in isRegOrImmWithInputMods()
7505 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) { in cvtVOP3Interp()
7509 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3Interp()
7513 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3Interp()
7528 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) { in cvtVOP3()
7554 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3()
7558 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3()
7566 if (Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || in cvtVOP3()
7567 Opc == AMDGPU::V_MAC_F32_e64_gfx10 || in cvtVOP3()
7568 Opc == AMDGPU::V_MAC_F32_e64_vi || in cvtVOP3()
7569 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || in cvtVOP3()
7570 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || in cvtVOP3()
7571 Opc == AMDGPU::V_MAC_F16_e64_vi || in cvtVOP3()
7572 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a || in cvtVOP3()
7573 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 || in cvtVOP3()
7574 Opc == AMDGPU::V_FMAC_F32_e64_vi || in cvtVOP3()
7575 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || in cvtVOP3()
7576 Opc == AMDGPU::V_FMAC_F16_e64_gfx10) { in cvtVOP3()
7578 std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers)); in cvtVOP3()
7598 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) { in cvtVOP3P()
7606 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3P()
7611 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in cvtVOP3P()
7618 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo); in cvtVOP3P()
7624 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3P()
7625 AMDGPU::OpName::src1, in cvtVOP3P()
7626 AMDGPU::OpName::src2 }; in cvtVOP3P()
7627 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVOP3P()
7628 AMDGPU::OpName::src1_modifiers, in cvtVOP3P()
7629 AMDGPU::OpName::src2_modifiers }; in cvtVOP3P()
7643 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi); in cvtVOP3P()
7649 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVOP3P()
7667 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVOP3P()
7688 using namespace AMDGPU::DPP; in isDPPCtrl()
7760 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId); in parseDimId()
7887 using namespace AMDGPU::DPP; in parseDPPCtrlSel()
7935 using namespace AMDGPU::DPP; in parseDPPCtrl()
7994 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1; in cvtDPP()
8049 using namespace llvm::AMDGPU::DPP; in cvtDPP()
8055 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) { in cvtDPP()
8068 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
8102 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
8154 using namespace llvm::AMDGPU::SDWA; in cvtSDWA()
8169 (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) { in cvtSDWA()
8197 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 && in cvtSDWA()
8198 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 && in cvtSDWA()
8199 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) { in cvtSDWA()
8204 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
8214 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
8224 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1) in cvtSDWA()
8237 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in cvtSDWA()
8238 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in cvtSDWA()
8241 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2)); in cvtSDWA()