Lines Matching refs:Root
3226 AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const { in selectVCSRC()
3228 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
3234 AMDGPUInstructionSelector::selectVOP3ModsImpl(MachineOperand &Root, in selectVOP3ModsImpl() argument
3236 Register Src = Root.getReg(); in selectVOP3ModsImpl()
3254 MachineInstr *UseMI = Root.getParent(); in selectVOP3ModsImpl()
3273 AMDGPUInstructionSelector::selectVSRC0(MachineOperand &Root) const { in selectVSRC0()
3275 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
3280 AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const { in selectVOP3Mods0()
3283 std::tie(Src, Mods) = selectVOP3ModsImpl(Root); in selectVOP3Mods0()
3294 AMDGPUInstructionSelector::selectVOP3BMods0(MachineOperand &Root) const { in selectVOP3BMods0()
3297 std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /* AllowAbs */ false); in selectVOP3BMods0()
3308 AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const { in selectVOP3OMods()
3310 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectVOP3OMods()
3317 AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const { in selectVOP3Mods()
3320 std::tie(Src, Mods) = selectVOP3ModsImpl(Root); in selectVOP3Mods()
3329 AMDGPUInstructionSelector::selectVOP3BMods(MachineOperand &Root) const { in selectVOP3BMods()
3332 std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /* AllowAbs */ false); in selectVOP3BMods()
3341 AMDGPUInstructionSelector::selectVOP3NoMods(MachineOperand &Root) const { in selectVOP3NoMods()
3342 Register Reg = Root.getReg(); in selectVOP3NoMods()
3376 AMDGPUInstructionSelector::selectVOP3PMods(MachineOperand &Root) const { in selectVOP3PMods()
3378 = Root.getParent()->getParent()->getParent()->getRegInfo(); in selectVOP3PMods()
3382 std::tie(Src, Mods) = selectVOP3PModsImpl(Root.getReg(), MRI); in selectVOP3PMods()
3391 AMDGPUInstructionSelector::selectVOP3Mods_nnan(MachineOperand &Root) const { in selectVOP3Mods_nnan()
3394 std::tie(Src, Mods) = selectVOP3ModsImpl(Root); in selectVOP3Mods_nnan()
3405 AMDGPUInstructionSelector::selectVOP3OpSelMods(MachineOperand &Root) const { in selectVOP3OpSelMods()
3408 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, in selectVOP3OpSelMods()
3414 AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const { in selectSmrdImm()
3416 getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo); in selectSmrdImm()
3435 AMDGPUInstructionSelector::selectSmrdImm32(MachineOperand &Root) const { in selectSmrdImm32()
3437 getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo); in selectSmrdImm32()
3456 AMDGPUInstructionSelector::selectSmrdSgpr(MachineOperand &Root) const { in selectSmrdSgpr()
3457 MachineInstr *MI = Root.getParent(); in selectSmrdSgpr()
3488 AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root, in selectFlatOffsetImpl() argument
3490 MachineInstr *MI = Root.getParent(); in selectFlatOffsetImpl()
3492 auto Default = std::make_pair(Root.getReg(), 0); in selectFlatOffsetImpl()
3500 getPtrBaseWithConstantOffset(Root.getReg(), *MRI); in selectFlatOffsetImpl()
3512 AMDGPUInstructionSelector::selectFlatOffset(MachineOperand &Root) const { in selectFlatOffset()
3513 auto PtrWithOffset = selectFlatOffsetImpl(Root, SIInstrFlags::FLAT); in selectFlatOffset()
3522 AMDGPUInstructionSelector::selectGlobalOffset(MachineOperand &Root) const { in selectGlobalOffset()
3523 auto PtrWithOffset = selectFlatOffsetImpl(Root, SIInstrFlags::FlatGlobal); in selectGlobalOffset()
3532 AMDGPUInstructionSelector::selectScratchOffset(MachineOperand &Root) const { in selectScratchOffset()
3533 auto PtrWithOffset = selectFlatOffsetImpl(Root, SIInstrFlags::FlatScratch); in selectScratchOffset()
3561 AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const { in selectGlobalSAddr()
3562 Register Addr = Root.getReg(); in selectGlobalSAddr()
3593 MachineInstr *MI = Root.getParent(); in selectGlobalSAddr()
3663 MachineInstr *MI = Root.getParent(); in selectGlobalSAddr()
3678 AMDGPUInstructionSelector::selectScratchSAddr(MachineOperand &Root) const { in selectScratchSAddr()
3679 Register Addr = Root.getReg(); in selectScratchSAddr()
3719 MachineInstr &I = *Root.getParent(); in selectScratchSAddr()
3740 AMDGPUInstructionSelector::selectMUBUFScratchOffen(MachineOperand &Root) const { in selectMUBUFScratchOffen()
3741 MachineInstr *MI = Root.getParent(); in selectMUBUFScratchOffen()
3747 if (mi_match(Root.getReg(), *MRI, m_ICst(Offset)) && in selectMUBUFScratchOffen()
3778 Register VAddr = Root.getReg(); in selectMUBUFScratchOffen()
3779 if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) { in selectMUBUFScratchOffen()
3849 MachineOperand &Root) const { in selectMUBUFScratchOffset()
3850 MachineInstr *MI = Root.getParent(); in selectMUBUFScratchOffset()
3854 if (!mi_match(Root.getReg(), *MRI, m_ICst(Offset)) || in selectMUBUFScratchOffset()
3873 AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const { in selectDS1Addr1OffsetImpl()
3874 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDS1Addr1OffsetImpl()
3876 return std::make_pair(Root.getReg(), 0); in selectDS1Addr1OffsetImpl()
3883 getPtrBaseWithConstantOffset(Root.getReg(), *MRI); in selectDS1Addr1OffsetImpl()
3894 } else if (mi_match(Root.getReg(), *MRI, m_ICst(ConstAddr))) { in selectDS1Addr1OffsetImpl()
3899 return std::make_pair(Root.getReg(), 0); in selectDS1Addr1OffsetImpl()
3903 AMDGPUInstructionSelector::selectDS1Addr1Offset(MachineOperand &Root) const { in selectDS1Addr1Offset()
3906 std::tie(Reg, Offset) = selectDS1Addr1OffsetImpl(Root); in selectDS1Addr1Offset()
3914 AMDGPUInstructionSelector::selectDS64Bit4ByteAligned(MachineOperand &Root) const { in selectDS64Bit4ByteAligned()
3915 return selectDSReadWrite2(Root, 4); in selectDS64Bit4ByteAligned()
3919 AMDGPUInstructionSelector::selectDS128Bit8ByteAligned(MachineOperand &Root) const { in selectDS128Bit8ByteAligned()
3920 return selectDSReadWrite2(Root, 8); in selectDS128Bit8ByteAligned()
3924 AMDGPUInstructionSelector::selectDSReadWrite2(MachineOperand &Root, in selectDSReadWrite2() argument
3928 std::tie(Reg, Offset) = selectDSReadWrite2Impl(Root, Size); in selectDSReadWrite2()
3937 AMDGPUInstructionSelector::selectDSReadWrite2Impl(MachineOperand &Root, in selectDSReadWrite2Impl() argument
3939 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDSReadWrite2Impl()
3941 return std::make_pair(Root.getReg(), 0); in selectDSReadWrite2Impl()
3948 getPtrBaseWithConstantOffset(Root.getReg(), *MRI); in selectDSReadWrite2Impl()
3960 } else if (mi_match(Root.getReg(), *MRI, m_ICst(ConstAddr))) { in selectDSReadWrite2Impl()
3965 return std::make_pair(Root.getReg(), 0); in selectDSReadWrite2Impl()
3974 Register Root, const MachineRegisterInfo &MRI) const { in getPtrBaseWithConstantOffset() argument
3975 MachineInstr *RootI = getDefIgnoringCopies(Root, MRI); in getPtrBaseWithConstantOffset()
3977 return {Root, 0}; in getPtrBaseWithConstantOffset()
3983 return {Root, 0}; in getPtrBaseWithConstantOffset()
4113 MachineOperand &Root, Register &VAddr, Register &RSrcReg, in selectMUBUFAddr64Impl() argument
4120 MUBUFAddressData AddrData = parseMUBUFAddress(Root.getReg()); in selectMUBUFAddr64Impl()
4157 MachineIRBuilder B(*Root.getParent()); in selectMUBUFAddr64Impl()
4164 MachineOperand &Root, Register &RSrcReg, Register &SOffset, in selectMUBUFOffsetImpl() argument
4171 MUBUFAddressData AddrData = parseMUBUFAddress(Root.getReg()); in selectMUBUFOffsetImpl()
4181 MachineIRBuilder B(*Root.getParent()); in selectMUBUFOffsetImpl()
4189 AMDGPUInstructionSelector::selectMUBUFAddr64(MachineOperand &Root) const { in selectMUBUFAddr64()
4195 if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset)) in selectMUBUFAddr64()
4223 AMDGPUInstructionSelector::selectMUBUFOffset(MachineOperand &Root) const { in selectMUBUFOffset()
4228 if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset)) in selectMUBUFOffset()
4249 AMDGPUInstructionSelector::selectMUBUFAddr64Atomic(MachineOperand &Root) const { in selectMUBUFAddr64Atomic()
4255 if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset)) in selectMUBUFAddr64Atomic()
4283 AMDGPUInstructionSelector::selectMUBUFOffsetAtomic(MachineOperand &Root) const { in selectMUBUFOffsetAtomic()
4288 if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset)) in selectMUBUFOffsetAtomic()
4317 AMDGPUInstructionSelector::selectSMRDBufferImm(MachineOperand &Root) const { in selectSMRDBufferImm()
4318 Optional<uint64_t> OffsetVal = getConstantZext32Val(Root.getReg(), *MRI); in selectSMRDBufferImm()
4331 AMDGPUInstructionSelector::selectSMRDBufferImm32(MachineOperand &Root) const { in selectSMRDBufferImm32()
4334 Optional<uint64_t> OffsetVal = getConstantZext32Val(Root.getReg(), *MRI); in selectSMRDBufferImm32()