Lines Matching refs:MachineInstrBuilder
522 MachineInstrBuilder MIB = in selectG_MERGE_VALUES()
1307 MachineInstrBuilder DS = in selectDSOrderedIntrinsic()
3228 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
3275 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
3286 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods0()
3287 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3Mods0()
3288 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3Mods0()
3289 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3Mods0()
3300 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3BMods0()
3301 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3BMods0()
3302 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3BMods0()
3303 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3BMods0()
3310 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectVOP3OMods()
3311 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3OMods()
3312 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3OMods()
3323 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods()
3324 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods()
3335 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3BMods()
3336 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3BMods()
3348 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3385 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3386 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMods()
3399 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods_nnan()
3400 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods_nnan()
3408 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, in selectVOP3OpSelMods()
3409 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods in selectVOP3OpSelMods()
3429 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm()
3430 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } in selectSmrdImm()
3450 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
3451 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } in selectSmrdImm32()
3482 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdSgpr()
3483 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); } in selectSmrdSgpr()
3516 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
3517 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectFlatOffset()
3526 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
3527 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectGlobalOffset()
3536 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
3537 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectScratchOffset()
3603 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
3604 [=](MachineInstrBuilder &MIB) { in selectGlobalSAddr()
3607 [=](MachineInstrBuilder &MIB) { MIB.addImm(SplitImmOffset); }, in selectGlobalSAddr()
3642 return {{[=](MachineInstrBuilder &MIB) { // saddr in selectGlobalSAddr()
3645 [=](MachineInstrBuilder &MIB) { // voffset in selectGlobalSAddr()
3648 [=](MachineInstrBuilder &MIB) { // offset in selectGlobalSAddr()
3671 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
3672 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
3673 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectGlobalSAddr()
3702 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSAddr()
3703 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
3734 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
3735 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
3757 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
3760 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
3763 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
3768 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
3799 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
3802 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
3808 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
3813 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
3862 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
3865 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
3868 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
3908 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
3909 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } in selectDS1Addr1Offset()
3930 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
3931 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, in selectDSReadWrite2()
3932 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); } in selectDSReadWrite2()
3987 static void addZeroImm(MachineInstrBuilder &MIB) { in addZeroImm()
4201 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFAddr64()
4204 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFAddr64()
4207 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFAddr64()
4213 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFAddr64()
4232 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFOffset()
4235 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFOffset()
4241 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffset()
4261 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFAddr64Atomic()
4264 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFAddr64Atomic()
4267 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFAddr64Atomic()
4273 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFAddr64Atomic()
4276 [=](MachineInstrBuilder &MIB) { in selectMUBUFAddr64Atomic()
4292 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFOffsetAtomic()
4295 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFOffsetAtomic()
4301 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffsetAtomic()
4302 [=](MachineInstrBuilder &MIB) { MIB.addImm(AMDGPU::CPol::GLC); } // cpol in selectMUBUFOffsetAtomic()
4327 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm()
4343 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm32()
4346 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB, in renderTruncImm32()
4354 void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB, in renderNegateImm()
4362 void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB, in renderBitcastImm()
4376 void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB, in renderPopcntImm()
4386 void AMDGPUInstructionSelector::renderTruncTImm(MachineInstrBuilder &MIB, in renderTruncTImm()
4392 void AMDGPUInstructionSelector::renderExtractCPol(MachineInstrBuilder &MIB, in renderExtractCPol()
4399 void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB, in renderExtractSWZ()
4406 void AMDGPUInstructionSelector::renderSetGLC(MachineInstrBuilder &MIB, in renderSetGLC()
4413 void AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB, in renderFrameIndex()