266 static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) {  in getLogicalBitOpcode()  argument
269     return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;  in getLogicalBitOpcode()
271     return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32;  in getLogicalBitOpcode()
273     return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32;  in getLogicalBitOpcode()
288   bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&  in selectG_AND_OR_XOR()  local
290   I.setDesc(TII.get(getLogicalBitOpcode(I.getOpcode(), Is64)));  in selectG_AND_OR_XOR()
1127   const bool Is64 = Size == 64;  in selectBallot()  local
1138       unsigned Opcode = Is64 ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;  in selectBallot()
1141       Register SrcReg = Is64 ? AMDGPU::EXEC : AMDGPU::EXEC_LO;  in selectBallot()
1685       const bool Is64 = MRI->getType(VDataOut).getSizeInBits() == 64;  in selectImageIntrinsic()  local
1688         Is64 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass);  in selectImageIntrinsic()
1689       unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;  in selectImageIntrinsic()
2420   const bool Is64 = Ty.getSizeInBits() == 64;  in selectG_AMDGPU_ATOMIC_CMPXCHG()  local
2421   const unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;  in selectG_AMDGPU_ATOMIC_CMPXCHG()
2423     Is64 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass);  in selectG_AMDGPU_ATOMIC_CMPXCHG()
2433     Opcode = Is64 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN :  in selectG_AMDGPU_ATOMIC_CMPXCHG()
2437     Opcode = Is64 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN :  in selectG_AMDGPU_ATOMIC_CMPXCHG()
2464     DstReg, Is64 ? &AMDGPU::VReg_64RegClass : &AMDGPU::VGPR_32RegClass);  in selectG_AMDGPU_ATOMIC_CMPXCHG()
2683   const bool Is64 = DstTy.getSizeInBits() == 64;  in selectG_EXTRACT_VECTOR_ELT()  local
2690     if (DstTy.getSizeInBits() != 32 && !Is64)  in selectG_EXTRACT_VECTOR_ELT()
2696     unsigned Opc = Is64 ? AMDGPU::S_MOVRELS_B64 : AMDGPU::S_MOVRELS_B32;  in selectG_EXTRACT_VECTOR_ELT()