966 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()  argument
973   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;  in isNarrowingProfitable()
1420   EVT SrcVT = Op.getOperand(0).getValueType();  in LowerEXTRACT_SUBVECTOR()  local
1423   if (((SrcVT == MVT::v4f16 && VT == MVT::v2f16) ||  in LowerEXTRACT_SUBVECTOR()
1424        (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) &&  in LowerEXTRACT_SUBVECTOR()
2567   EVT SrcVT = Src.getValueType();  in LowerUINT_TO_FP()  local
2569   if (SrcVT == MVT::i16) {  in LowerUINT_TO_FP()
2579   assert(SrcVT == MVT::i64 && "operation should be legal");  in LowerUINT_TO_FP()
2604   EVT SrcVT = Src.getValueType();  in LowerSINT_TO_FP()  local
2606   if (SrcVT == MVT::i16) {  in LowerSINT_TO_FP()
2616   assert(SrcVT == MVT::i64 && "operation should be legal");  in LowerSINT_TO_FP()
2644   EVT SrcVT = Src.getValueType();  in LowerFP_TO_INT64()  local
2646   assert(SrcVT == MVT::f32 || SrcVT == MVT::f64);  in LowerFP_TO_INT64()
2657   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src);  in LowerFP_TO_INT64()
2659   if (Signed && SrcVT == MVT::f32) {  in LowerFP_TO_INT64()
2668     Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc);  in LowerFP_TO_INT64()
2672   if (SrcVT == MVT::f64) {  in LowerFP_TO_INT64()
2674                            SL, SrcVT);  in LowerFP_TO_INT64()
2676                            SL, SrcVT);  in LowerFP_TO_INT64()
2679                            SrcVT);  in LowerFP_TO_INT64()
2681                            SrcVT);  in LowerFP_TO_INT64()
2684   SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0);  in LowerFP_TO_INT64()
2686   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul);  in LowerFP_TO_INT64()
2688   SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc);  in LowerFP_TO_INT64()
2690   SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT  in LowerFP_TO_INT64()
2698   if (Signed && SrcVT == MVT::f32) {  in LowerFP_TO_INT64()
2815   EVT SrcVT = Src.getValueType();  in LowerFP_TO_INT()  local
2819   if (SrcVT == MVT::f16 && DestVT == MVT::i16)  in LowerFP_TO_INT()
2823   if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {  in LowerFP_TO_INT()
2830   if (SrcVT == MVT::f16 ||  in LowerFP_TO_INT()
2831       (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) {  in LowerFP_TO_INT()
2840   if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64))  in LowerFP_TO_INT()
3089     EVT SrcVT = Src.getValueType();  in performAssertSZExtCombine()  local
3090     if (SrcVT.bitsGE(ExtVT)) {  in performAssertSZExtCombine()
3091       SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);  in performAssertSZExtCombine()
3349     EVT SrcVT = Src.getValueType();  in performTruncateCombine()  local
3350     if (SrcVT.getScalarSizeInBits() > 32 &&  in performTruncateCombine()
3960     EVT SrcVT = Src.getValueType();  in performFNegCombine()  local
3963     SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,  in performFNegCombine()
3964                                   DAG.getConstant(0x8000, SL, SrcVT));  in performFNegCombine()
3985     EVT SrcVT = Src.getValueType();  in performFAbsCombine()  local
3988     SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,  in performFAbsCombine()
3989                                   DAG.getConstant(0x7fff, SL, SrcVT));  in performFAbsCombine()
4028         EVT SrcVT = Src.getValueType();  in PerformDAGCombine()  local
4031         if (SrcVT.getVectorNumElements() == NElts) {  in PerformDAGCombine()
4036           for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {  in PerformDAGCombine()