Lines Matching refs:MVT
44 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
66 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
67 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
69 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
70 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
72 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
73 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
75 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
79 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
81 setOperationAction(ISD::LOAD, MVT::v6f32, Promote); in AMDGPUTargetLowering()
82 AddPromotedToType(ISD::LOAD, MVT::v6f32, MVT::v6i32); in AMDGPUTargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v7f32, Promote); in AMDGPUTargetLowering()
85 AddPromotedToType(ISD::LOAD, MVT::v7f32, MVT::v7i32); in AMDGPUTargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
88 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
90 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
91 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
93 setOperationAction(ISD::LOAD, MVT::v32f32, Promote); in AMDGPUTargetLowering()
94 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
96 setOperationAction(ISD::LOAD, MVT::i64, Promote); in AMDGPUTargetLowering()
97 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
99 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in AMDGPUTargetLowering()
100 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32); in AMDGPUTargetLowering()
102 setOperationAction(ISD::LOAD, MVT::f64, Promote); in AMDGPUTargetLowering()
103 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
105 setOperationAction(ISD::LOAD, MVT::v2f64, Promote); in AMDGPUTargetLowering()
106 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32); in AMDGPUTargetLowering()
108 setOperationAction(ISD::LOAD, MVT::v3i64, Promote); in AMDGPUTargetLowering()
109 AddPromotedToType(ISD::LOAD, MVT::v3i64, MVT::v6i32); in AMDGPUTargetLowering()
111 setOperationAction(ISD::LOAD, MVT::v4i64, Promote); in AMDGPUTargetLowering()
112 AddPromotedToType(ISD::LOAD, MVT::v4i64, MVT::v8i32); in AMDGPUTargetLowering()
114 setOperationAction(ISD::LOAD, MVT::v3f64, Promote); in AMDGPUTargetLowering()
115 AddPromotedToType(ISD::LOAD, MVT::v3f64, MVT::v6i32); in AMDGPUTargetLowering()
117 setOperationAction(ISD::LOAD, MVT::v4f64, Promote); in AMDGPUTargetLowering()
118 AddPromotedToType(ISD::LOAD, MVT::v4f64, MVT::v8i32); in AMDGPUTargetLowering()
120 setOperationAction(ISD::LOAD, MVT::v8i64, Promote); in AMDGPUTargetLowering()
121 AddPromotedToType(ISD::LOAD, MVT::v8i64, MVT::v16i32); in AMDGPUTargetLowering()
123 setOperationAction(ISD::LOAD, MVT::v8f64, Promote); in AMDGPUTargetLowering()
124 AddPromotedToType(ISD::LOAD, MVT::v8f64, MVT::v16i32); in AMDGPUTargetLowering()
126 setOperationAction(ISD::LOAD, MVT::v16i64, Promote); in AMDGPUTargetLowering()
127 AddPromotedToType(ISD::LOAD, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
129 setOperationAction(ISD::LOAD, MVT::v16f64, Promote); in AMDGPUTargetLowering()
130 AddPromotedToType(ISD::LOAD, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
134 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering()
135 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
140 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering()
141 if (VT == MVT::i64) in AMDGPUTargetLowering()
144 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
146 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
147 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
150 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
151 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
152 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
154 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
155 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
156 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
157 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
160 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { in AMDGPUTargetLowering()
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
162 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
163 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
164 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
165 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
166 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
167 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
168 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
169 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
170 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
171 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
172 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
173 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
174 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
175 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
178 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
179 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
180 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand); in AMDGPUTargetLowering()
181 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
182 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
183 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
184 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
186 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in AMDGPUTargetLowering()
187 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
188 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f32, Expand); in AMDGPUTargetLowering()
189 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in AMDGPUTargetLowering()
190 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand); in AMDGPUTargetLowering()
191 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
193 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in AMDGPUTargetLowering()
194 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in AMDGPUTargetLowering()
195 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f16, Expand); in AMDGPUTargetLowering()
196 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
197 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand); in AMDGPUTargetLowering()
198 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f16, Expand); in AMDGPUTargetLowering()
200 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
201 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
203 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
204 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
206 setOperationAction(ISD::STORE, MVT::v3f32, Promote); in AMDGPUTargetLowering()
207 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
209 setOperationAction(ISD::STORE, MVT::v4f32, Promote); in AMDGPUTargetLowering()
210 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
212 setOperationAction(ISD::STORE, MVT::v5f32, Promote); in AMDGPUTargetLowering()
213 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
215 setOperationAction(ISD::STORE, MVT::v6f32, Promote); in AMDGPUTargetLowering()
216 AddPromotedToType(ISD::STORE, MVT::v6f32, MVT::v6i32); in AMDGPUTargetLowering()
218 setOperationAction(ISD::STORE, MVT::v7f32, Promote); in AMDGPUTargetLowering()
219 AddPromotedToType(ISD::STORE, MVT::v7f32, MVT::v7i32); in AMDGPUTargetLowering()
221 setOperationAction(ISD::STORE, MVT::v8f32, Promote); in AMDGPUTargetLowering()
222 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
224 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
225 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
227 setOperationAction(ISD::STORE, MVT::v32f32, Promote); in AMDGPUTargetLowering()
228 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
230 setOperationAction(ISD::STORE, MVT::i64, Promote); in AMDGPUTargetLowering()
231 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
233 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in AMDGPUTargetLowering()
234 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32); in AMDGPUTargetLowering()
236 setOperationAction(ISD::STORE, MVT::f64, Promote); in AMDGPUTargetLowering()
237 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
239 setOperationAction(ISD::STORE, MVT::v2f64, Promote); in AMDGPUTargetLowering()
240 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32); in AMDGPUTargetLowering()
242 setOperationAction(ISD::STORE, MVT::v3i64, Promote); in AMDGPUTargetLowering()
243 AddPromotedToType(ISD::STORE, MVT::v3i64, MVT::v6i32); in AMDGPUTargetLowering()
245 setOperationAction(ISD::STORE, MVT::v3f64, Promote); in AMDGPUTargetLowering()
246 AddPromotedToType(ISD::STORE, MVT::v3f64, MVT::v6i32); in AMDGPUTargetLowering()
248 setOperationAction(ISD::STORE, MVT::v4i64, Promote); in AMDGPUTargetLowering()
249 AddPromotedToType(ISD::STORE, MVT::v4i64, MVT::v8i32); in AMDGPUTargetLowering()
251 setOperationAction(ISD::STORE, MVT::v4f64, Promote); in AMDGPUTargetLowering()
252 AddPromotedToType(ISD::STORE, MVT::v4f64, MVT::v8i32); in AMDGPUTargetLowering()
254 setOperationAction(ISD::STORE, MVT::v8i64, Promote); in AMDGPUTargetLowering()
255 AddPromotedToType(ISD::STORE, MVT::v8i64, MVT::v16i32); in AMDGPUTargetLowering()
257 setOperationAction(ISD::STORE, MVT::v8f64, Promote); in AMDGPUTargetLowering()
258 AddPromotedToType(ISD::STORE, MVT::v8f64, MVT::v16i32); in AMDGPUTargetLowering()
260 setOperationAction(ISD::STORE, MVT::v16i64, Promote); in AMDGPUTargetLowering()
261 AddPromotedToType(ISD::STORE, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
263 setOperationAction(ISD::STORE, MVT::v16f64, Promote); in AMDGPUTargetLowering()
264 AddPromotedToType(ISD::STORE, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
266 setTruncStoreAction(MVT::i64, MVT::i1, Expand); in AMDGPUTargetLowering()
267 setTruncStoreAction(MVT::i64, MVT::i8, Expand); in AMDGPUTargetLowering()
268 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in AMDGPUTargetLowering()
269 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in AMDGPUTargetLowering()
271 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand); in AMDGPUTargetLowering()
272 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand); in AMDGPUTargetLowering()
273 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand); in AMDGPUTargetLowering()
274 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand); in AMDGPUTargetLowering()
276 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
277 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
278 setTruncStoreAction(MVT::v3f32, MVT::v3f16, Expand); in AMDGPUTargetLowering()
279 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
280 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
281 setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
282 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
284 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in AMDGPUTargetLowering()
285 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in AMDGPUTargetLowering()
287 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
288 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand); in AMDGPUTargetLowering()
290 setTruncStoreAction(MVT::v3i64, MVT::v3i32, Expand); in AMDGPUTargetLowering()
291 setTruncStoreAction(MVT::v3i64, MVT::v3i16, Expand); in AMDGPUTargetLowering()
292 setTruncStoreAction(MVT::v3f64, MVT::v3f32, Expand); in AMDGPUTargetLowering()
293 setTruncStoreAction(MVT::v3f64, MVT::v3f16, Expand); in AMDGPUTargetLowering()
295 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Expand); in AMDGPUTargetLowering()
296 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Expand); in AMDGPUTargetLowering()
297 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand); in AMDGPUTargetLowering()
298 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
300 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand); in AMDGPUTargetLowering()
301 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand); in AMDGPUTargetLowering()
303 setTruncStoreAction(MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
304 setTruncStoreAction(MVT::v16f64, MVT::v16f16, Expand); in AMDGPUTargetLowering()
305 setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand); in AMDGPUTargetLowering()
306 setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand); in AMDGPUTargetLowering()
307 setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand); in AMDGPUTargetLowering()
308 setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand); in AMDGPUTargetLowering()
309 setTruncStoreAction(MVT::v16i64, MVT::v16i1, Expand); in AMDGPUTargetLowering()
311 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
312 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
313 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
314 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
316 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
317 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
320 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in AMDGPUTargetLowering()
324 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
325 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
326 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
327 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
328 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
329 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
330 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
331 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
332 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
333 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
335 setOperationAction(ISD::FROUND, MVT::f32, Custom); in AMDGPUTargetLowering()
336 setOperationAction(ISD::FROUND, MVT::f64, Custom); in AMDGPUTargetLowering()
338 setOperationAction(ISD::FLOG, MVT::f32, Custom); in AMDGPUTargetLowering()
339 setOperationAction(ISD::FLOG10, MVT::f32, Custom); in AMDGPUTargetLowering()
340 setOperationAction(ISD::FEXP, MVT::f32, Custom); in AMDGPUTargetLowering()
343 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); in AMDGPUTargetLowering()
344 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom); in AMDGPUTargetLowering()
346 setOperationAction(ISD::FREM, MVT::f16, Custom); in AMDGPUTargetLowering()
347 setOperationAction(ISD::FREM, MVT::f32, Custom); in AMDGPUTargetLowering()
348 setOperationAction(ISD::FREM, MVT::f64, Custom); in AMDGPUTargetLowering()
351 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
353 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom); in AMDGPUTargetLowering()
354 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom); in AMDGPUTargetLowering()
355 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); in AMDGPUTargetLowering()
358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); in AMDGPUTargetLowering()
359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v6i32, Custom); in AMDGPUTargetLowering()
360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v6f32, Custom); in AMDGPUTargetLowering()
361 setOperationAction(ISD::CONCAT_VECTORS, MVT::v7i32, Custom); in AMDGPUTargetLowering()
362 setOperationAction(ISD::CONCAT_VECTORS, MVT::v7f32, Custom); in AMDGPUTargetLowering()
363 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
364 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
365 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f16, Custom); in AMDGPUTargetLowering()
366 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i16, Custom); in AMDGPUTargetLowering()
367 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
368 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
369 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom); in AMDGPUTargetLowering()
370 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); in AMDGPUTargetLowering()
371 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
372 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
373 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
374 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
375 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v6f32, Custom); in AMDGPUTargetLowering()
376 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v6i32, Custom); in AMDGPUTargetLowering()
377 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v7f32, Custom); in AMDGPUTargetLowering()
378 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v7i32, Custom); in AMDGPUTargetLowering()
379 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
380 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
381 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom); in AMDGPUTargetLowering()
382 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom); in AMDGPUTargetLowering()
383 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom); in AMDGPUTargetLowering()
384 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom); in AMDGPUTargetLowering()
385 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f64, Custom); in AMDGPUTargetLowering()
386 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64, Custom); in AMDGPUTargetLowering()
387 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f64, Custom); in AMDGPUTargetLowering()
388 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i64, Custom); in AMDGPUTargetLowering()
389 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f64, Custom); in AMDGPUTargetLowering()
390 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i64, Custom); in AMDGPUTargetLowering()
391 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f64, Custom); in AMDGPUTargetLowering()
392 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i64, Custom); in AMDGPUTargetLowering()
393 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f64, Custom); in AMDGPUTargetLowering()
394 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i64, Custom); in AMDGPUTargetLowering()
396 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in AMDGPUTargetLowering()
397 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in AMDGPUTargetLowering()
398 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in AMDGPUTargetLowering()
400 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in AMDGPUTargetLowering()
401 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering()
428 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()
431 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AMDGPUTargetLowering()
432 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AMDGPUTargetLowering()
433 setOperationAction(ISD::ROTR, MVT::i64, Expand); in AMDGPUTargetLowering()
435 setOperationAction(ISD::MULHU, MVT::i16, Expand); in AMDGPUTargetLowering()
436 setOperationAction(ISD::MULHS, MVT::i16, Expand); in AMDGPUTargetLowering()
438 setOperationAction(ISD::MUL, MVT::i64, Expand); in AMDGPUTargetLowering()
439 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
440 setOperationAction(ISD::MULHS, MVT::i64, Expand); in AMDGPUTargetLowering()
441 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
442 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
443 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
444 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in AMDGPUTargetLowering()
445 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AMDGPUTargetLowering()
447 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AMDGPUTargetLowering()
448 setOperationAction(ISD::UMIN, MVT::i32, Legal); in AMDGPUTargetLowering()
449 setOperationAction(ISD::SMAX, MVT::i32, Legal); in AMDGPUTargetLowering()
450 setOperationAction(ISD::UMAX, MVT::i32, Legal); in AMDGPUTargetLowering()
452 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in AMDGPUTargetLowering()
453 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
454 setOperationAction(ISD::CTLZ, MVT::i64, Custom); in AMDGPUTargetLowering()
455 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
457 static const MVT::SimpleValueType VectorIntTypes[] = { in AMDGPUTargetLowering()
458 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32}; in AMDGPUTargetLowering()
460 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering()
498 static const MVT::SimpleValueType FloatVectorTypes[] = { in AMDGPUTargetLowering()
499 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32, MVT::v6f32, MVT::v7f32}; in AMDGPUTargetLowering()
501 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering()
537 setOperationAction(ISD::SELECT, MVT::v2f32, Promote); in AMDGPUTargetLowering()
538 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
540 setOperationAction(ISD::SELECT, MVT::v3f32, Promote); in AMDGPUTargetLowering()
541 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
543 setOperationAction(ISD::SELECT, MVT::v4f32, Promote); in AMDGPUTargetLowering()
544 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
546 setOperationAction(ISD::SELECT, MVT::v5f32, Promote); in AMDGPUTargetLowering()
547 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
549 setOperationAction(ISD::SELECT, MVT::v6f32, Promote); in AMDGPUTargetLowering()
550 AddPromotedToType(ISD::SELECT, MVT::v6f32, MVT::v6i32); in AMDGPUTargetLowering()
552 setOperationAction(ISD::SELECT, MVT::v7f32, Promote); in AMDGPUTargetLowering()
553 AddPromotedToType(ISD::SELECT, MVT::v7f32, MVT::v7i32); in AMDGPUTargetLowering()
666 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) { in opMustUseVOP3Encoding()
667 return N->getNumOperands() > 2 || VT == MVT::f64; in opMustUseVOP3Encoding()
717 MVT VT = N->getValueType(0).getScalarType().getSimpleVT(); in allUsesHaveSourceMods()
740 return MVT::i32; in getTypeForExtReturn()
744 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
745 return MVT::i32; in getVectorIdxTy()
757 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 || in isFPImmLegal()
758 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); in isFPImmLegal()
764 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64); in ShouldShrinkFPConstant()
812 if (LoadTy.getScalarType() == MVT::i32) in isLoadBitCastBeneficial()
890 return VT == MVT::f32 || VT == MVT::f64 || in isFAbsFree()
891 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()
898 return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f16; in isFNegFree()
956 if (Src == MVT::i16) in isZExtFree()
957 return Dest == MVT::i32 ||Dest == MVT::i64 ; in isZExtFree()
959 return Src == MVT::i32 && Dest == MVT::i64; in isZExtFree()
1101 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute()
1181 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
1232 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
1369 SDValue Trap = DAG.getNode(ISD::TRAP, DL, MVT::Other, DAG.getEntryNode()); in LowerGlobalAddress()
1370 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, in LowerGlobalAddress()
1399 if (VT == MVT::v4i16 || VT == MVT::v4f16) { in LowerCONCAT_VECTORS()
1401 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0)); in LowerCONCAT_VECTORS()
1402 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1)); in LowerCONCAT_VECTORS()
1404 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi }); in LowerCONCAT_VECTORS()
1423 if (((SrcVT == MVT::v4f16 && VT == MVT::v2f16) || in LowerEXTRACT_SUBVECTOR()
1424 (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) && in LowerEXTRACT_SUBVECTOR()
1512 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1514 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in split64BitValue()
1515 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in split64BitValue()
1517 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1518 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1526 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1527 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in getLoHalf64()
1528 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1534 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1535 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in getHiHalf64()
1536 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1627 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1705 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
1717 MVT IntVT = MVT::i32; in LowerDIVREM24()
1718 MVT FltVT = MVT::f32; in LowerDIVREM24()
1828 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64"); in LowerUDIVREM64()
1850 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero}); in LowerUDIVREM64()
1851 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero}); in LowerUDIVREM64()
1853 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV)); in LowerUDIVREM64()
1854 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM)); in LowerUDIVREM64()
1858 if (isTypeLegal(MVT::i64)) { in LowerUDIVREM64()
1869 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
1870 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
1871 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
1872 DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32), in LowerUDIVREM64()
1874 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64()
1875 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
1876 DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32)); in LowerUDIVREM64()
1877 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64()
1878 DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32)); in LowerUDIVREM64()
1879 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
1880 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
1881 DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32), in LowerUDIVREM64()
1886 DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi})); in LowerUDIVREM64()
1890 SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1); in LowerUDIVREM64()
1891 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1); in LowerUDIVREM64()
1907 DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi})); in LowerUDIVREM64()
1923 DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi})); in LowerUDIVREM64()
1936 DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi})); in LowerUDIVREM64()
1957 DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi})); in LowerUDIVREM64()
1977 DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi})); in LowerUDIVREM64()
2000 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero}); in LowerUDIVREM64()
2001 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM); in LowerUDIVREM64()
2031 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi}); in LowerUDIVREM64()
2032 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV); in LowerUDIVREM64()
2042 if (VT == MVT::i64) { in LowerUDIVREM()
2048 if (VT == MVT::i32) { in LowerUDIVREM()
2103 if (VT == MVT::i32) { in LowerSDIVREM()
2108 if (VT == MVT::i64 && in LowerSDIVREM()
2175 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2177 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFCEIL()
2178 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFCEIL()
2181 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64); in LowerFCEIL()
2187 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
2189 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2197 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in extractF64Exponent()
2199 DAG.getConstant(FractBits - 32, SL, MVT::i32), in extractF64Exponent()
2200 DAG.getConstant(ExpBits, SL, MVT::i32)); in extractF64Exponent()
2201 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2202 DAG.getConstant(1023, SL, MVT::i32)); in extractF64Exponent()
2211 assert(Op.getValueType() == MVT::f64); in LowerFTRUNC()
2213 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerFTRUNC()
2214 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerFTRUNC()
2216 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerFTRUNC()
2220 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2227 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32); in LowerFTRUNC()
2228 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2231 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2232 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2234 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2236 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64); in LowerFTRUNC()
2238 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2239 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
2240 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2243 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32); in LowerFTRUNC()
2245 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32); in LowerFTRUNC()
2250 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2251 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2253 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2260 assert(Op.getValueType() == MVT::f64); in LowerFRINT()
2263 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64); in LowerFRINT()
2264 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2268 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2269 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2271 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2274 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64); in LowerFRINT()
2277 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64); in LowerFRINT()
2280 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFRINT()
2332 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2334 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFFLOOR()
2335 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64); in LowerFFLOOR()
2338 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64); in LowerFFLOOR()
2344 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2346 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2397 if (ZeroUndef && Src.getValueType() == MVT::i32) in LowerCTLZ_CTTZ()
2398 return DAG.getNode(NewOpc, SL, MVT::i32, Src); in LowerCTLZ_CTTZ()
2400 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerCTLZ_CTTZ()
2402 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerCTLZ_CTTZ()
2403 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerCTLZ_CTTZ()
2405 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ_CTTZ()
2406 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ_CTTZ()
2409 *DAG.getContext(), MVT::i32); in LowerCTLZ_CTTZ()
2414 SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo); in LowerCTLZ_CTTZ()
2415 SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi); in LowerCTLZ_CTTZ()
2417 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ()
2420 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32); in LowerCTLZ_CTTZ()
2422 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi); in LowerCTLZ_CTTZ()
2424 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32); in LowerCTLZ_CTTZ()
2426 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo); in LowerCTLZ_CTTZ()
2443 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ()
2447 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, in LowerCTLZ_CTTZ()
2451 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
2481 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32()
2482 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
2484 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S); in LowerINT_TO_FP32()
2485 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S); in LowerINT_TO_FP32()
2489 *DAG.getContext(), MVT::f32); in LowerINT_TO_FP32()
2492 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32); in LowerINT_TO_FP32()
2493 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64); in LowerINT_TO_FP32()
2494 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L); in LowerINT_TO_FP32()
2495 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ); in LowerINT_TO_FP32()
2497 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32); in LowerINT_TO_FP32()
2498 SDValue E = DAG.getSelect(SL, MVT::i32, in LowerINT_TO_FP32()
2500 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ), in LowerINT_TO_FP32()
2503 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64, in LowerINT_TO_FP32()
2504 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ), in LowerINT_TO_FP32()
2505 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64)); in LowerINT_TO_FP32()
2507 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U, in LowerINT_TO_FP32()
2508 DAG.getConstant(0xffffffffffULL, SL, MVT::i64)); in LowerINT_TO_FP32()
2510 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64, in LowerINT_TO_FP32()
2511 U, DAG.getConstant(40, SL, MVT::i64)); in LowerINT_TO_FP32()
2513 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32, in LowerINT_TO_FP32()
2514 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)), in LowerINT_TO_FP32()
2515 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl)); in LowerINT_TO_FP32()
2517 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64); in LowerINT_TO_FP32()
2521 SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerINT_TO_FP32()
2523 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One); in LowerINT_TO_FP32()
2525 SDValue R = DAG.getSelect(SL, MVT::i32, in LowerINT_TO_FP32()
2528 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32)); in LowerINT_TO_FP32()
2529 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R); in LowerINT_TO_FP32()
2530 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R); in LowerINT_TO_FP32()
2535 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
2536 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R); in LowerINT_TO_FP32()
2544 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerINT_TO_FP64()
2546 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2547 DAG.getConstant(0, SL, MVT::i32)); in LowerINT_TO_FP64()
2548 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2549 DAG.getConstant(1, SL, MVT::i32)); in LowerINT_TO_FP64()
2552 SL, MVT::f64, Hi); in LowerINT_TO_FP64()
2554 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2556 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
2557 DAG.getConstant(32, SL, MVT::i32)); in LowerINT_TO_FP64()
2559 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
2569 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
2570 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
2575 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src); in LowerUINT_TO_FP()
2579 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerUINT_TO_FP()
2581 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()
2584 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src); in LowerUINT_TO_FP()
2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2592 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
2595 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
2606 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
2607 if (DestVT == MVT::f16) in LowerSINT_TO_FP()
2612 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, Src); in LowerSINT_TO_FP()
2616 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerSINT_TO_FP()
2620 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()
2624 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src); in LowerSINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
2632 if (DestVT == MVT::f32) in LowerSINT_TO_FP()
2635 assert(DestVT == MVT::f64); in LowerSINT_TO_FP()
2646 assert(SrcVT == MVT::f32 || SrcVT == MVT::f64); in LowerFP_TO_INT64()
2659 if (Signed && SrcVT == MVT::f32) { in LowerFP_TO_INT64()
2665 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
2666 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc), in LowerFP_TO_INT64()
2667 DAG.getConstant(31, SL, MVT::i32)); in LowerFP_TO_INT64()
2672 if (SrcVT == MVT::f64) { in LowerFP_TO_INT64()
2690 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
2692 SL, MVT::i32, FloorMul); in LowerFP_TO_INT64()
2693 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
2695 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
2696 DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi})); in LowerFP_TO_INT64()
2698 if (Signed && SrcVT == MVT::f32) { in LowerFP_TO_INT64()
2701 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
2702 DAG.getBuildVector(MVT::v2i32, SL, {Sign, Sign})); in LowerFP_TO_INT64()
2705 DAG.getNode(ISD::SUB, SL, MVT::i64, in LowerFP_TO_INT64()
2706 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign); in LowerFP_TO_INT64()
2717 if (N0.getValueType() == MVT::f32) in LowerFP_TO_FP16()
2725 assert(N0.getSimpleValueType() == MVT::f64); in LowerFP_TO_FP16()
2731 SDValue Zero = DAG.getConstant(0, DL, MVT::i32); in LowerFP_TO_FP16()
2732 SDValue One = DAG.getConstant(1, DL, MVT::i32); in LowerFP_TO_FP16()
2733 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0); in LowerFP_TO_FP16()
2734 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
2735 DAG.getConstant(32, DL, MVT::i64)); in LowerFP_TO_FP16()
2736 UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32); in LowerFP_TO_FP16()
2737 U = DAG.getZExtOrTrunc(U, DL, MVT::i32); in LowerFP_TO_FP16()
2738 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2739 DAG.getConstant(20, DL, MVT::i64)); in LowerFP_TO_FP16()
2740 E = DAG.getNode(ISD::AND, DL, MVT::i32, E, in LowerFP_TO_FP16()
2741 DAG.getConstant(ExpMask, DL, MVT::i32)); in LowerFP_TO_FP16()
2744 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E, in LowerFP_TO_FP16()
2745 DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32)); in LowerFP_TO_FP16()
2747 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2748 DAG.getConstant(8, DL, MVT::i32)); in LowerFP_TO_FP16()
2749 M = DAG.getNode(ISD::AND, DL, MVT::i32, M, in LowerFP_TO_FP16()
2750 DAG.getConstant(0xffe, DL, MVT::i32)); in LowerFP_TO_FP16()
2752 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2753 DAG.getConstant(0x1ff, DL, MVT::i32)); in LowerFP_TO_FP16()
2754 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U); in LowerFP_TO_FP16()
2757 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set); in LowerFP_TO_FP16()
2760 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32, in LowerFP_TO_FP16()
2761 DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32), in LowerFP_TO_FP16()
2762 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32)); in LowerFP_TO_FP16()
2765 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M, in LowerFP_TO_FP16()
2766 DAG.getNode(ISD::SHL, DL, MVT::i32, E, in LowerFP_TO_FP16()
2767 DAG.getConstant(12, DL, MVT::i32))); in LowerFP_TO_FP16()
2770 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32, in LowerFP_TO_FP16()
2772 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero); in LowerFP_TO_FP16()
2773 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B, in LowerFP_TO_FP16()
2774 DAG.getConstant(13, DL, MVT::i32)); in LowerFP_TO_FP16()
2776 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M, in LowerFP_TO_FP16()
2777 DAG.getConstant(0x1000, DL, MVT::i32)); in LowerFP_TO_FP16()
2779 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
2780 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B); in LowerFP_TO_FP16()
2782 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1); in LowerFP_TO_FP16()
2785 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V, in LowerFP_TO_FP16()
2786 DAG.getConstant(0x7, DL, MVT::i32)); in LowerFP_TO_FP16()
2787 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
2788 DAG.getConstant(2, DL, MVT::i32)); in LowerFP_TO_FP16()
2789 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32), in LowerFP_TO_FP16()
2791 SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32), in LowerFP_TO_FP16()
2793 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1); in LowerFP_TO_FP16()
2794 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1); in LowerFP_TO_FP16()
2796 V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32), in LowerFP_TO_FP16()
2797 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT); in LowerFP_TO_FP16()
2798 V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32), in LowerFP_TO_FP16()
2802 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2803 DAG.getConstant(16, DL, MVT::i32)); in LowerFP_TO_FP16()
2804 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign, in LowerFP_TO_FP16()
2805 DAG.getConstant(0x8000, DL, MVT::i32)); in LowerFP_TO_FP16()
2807 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V); in LowerFP_TO_FP16()
2819 if (SrcVT == MVT::f16 && DestVT == MVT::i16) in LowerFP_TO_INT()
2823 if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) { in LowerFP_TO_INT()
2826 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src); in LowerFP_TO_INT()
2827 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToInt32); in LowerFP_TO_INT()
2830 if (SrcVT == MVT::f16 || in LowerFP_TO_INT()
2831 (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) { in LowerFP_TO_INT()
2834 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src); in LowerFP_TO_INT()
2837 return DAG.getNode(Ext, DL, MVT::i64, FpToInt32); in LowerFP_TO_INT()
2840 if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) in LowerFP_TO_INT()
2849 MVT VT = Op.getSimpleValueType(); in LowerSIGN_EXTEND_INREG()
2850 MVT ScalarVT = VT.getScalarType(); in LowerSIGN_EXTEND_INREG()
2927 return DAG.getConstant(Result, DL, MVT::i32); in constantFoldBFE()
2930 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32); in constantFoldBFE()
2946 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT)) in shouldCombineMemoryType()
3131 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3132 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3134 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS); in splitBinaryBitConstantOpImpl()
3135 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS); in splitBinaryBitConstantOpImpl()
3142 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd}); in splitBinaryBitConstantOpImpl()
3143 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
3170 if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 && in performShlCombine()
3171 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) { in performShlCombine()
3174 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL, in performShlCombine()
3175 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) }); in performShlCombine()
3176 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
3180 if (VT != MVT::i64) in performShlCombine()
3192 if (VT != MVT::i64) in performShlCombine()
3203 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32); in performShlCombine()
3205 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3206 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
3208 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performShlCombine()
3210 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
3211 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
3216 if (N->getValueType(0) != MVT::i64) in performSraCombine()
3230 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3231 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3233 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
3234 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3240 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3241 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3242 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
3243 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3275 if (VT != MVT::i64) in performSrlCombine()
3284 SDValue One = DAG.getConstant(1, SL, MVT::i32); in performSrlCombine()
3285 SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performSrlCombine()
3287 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS); in performSrlCombine()
3288 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One); in performSrlCombine()
3290 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32); in performSrlCombine()
3291 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
3293 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
3295 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
3360 EVT::getVectorVT(*DAG.getContext(), MVT::i32, in performTruncateCombine()
3361 VT.getVectorNumElements()) : MVT::i32; in performTruncateCombine()
3391 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3397 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
3398 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
3400 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi); in getMul24()
3419 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
3441 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
3442 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32); in performMulCombine()
3445 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
3446 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32); in performMulCombine()
3482 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulhsCombine()
3483 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32); in performMulhsCombine()
3485 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1); in performMulhsCombine()
3515 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulhuCombine()
3516 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32); in performMulhuCombine()
3518 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1); in performMulhuCombine()
3535 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() && in getFFBX_U32()
3536 LegalVT != MVT::i16)) in getFFBX_U32()
3539 if (VT != MVT::i32) in getFFBX_U32()
3540 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op); in getFFBX_U32()
3542 SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op); in getFFBX_U32()
3543 if (VT != MVT::i32) in getFFBX_U32()
3706 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) { in performSelectCombine()
4057 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
4058 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
4059 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
4067 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
4068 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
4069 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
4123 return DAG.getConstant(0, DL, MVT::i32); in PerformDAGCombine()
4150 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
4175 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine()
4176 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
4262 SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32); in loadStackInputValue()
4278 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32); in storeStackInputValue()
4281 DAG.getCopyFromReg(Chain, SL, Info->getStackPtrOffsetReg(), MVT::i32); in storeStackInputValue()
4282 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr); in storeStackInputValue()
4486 if (VT == MVT::f32) { in getSqrtEstimate()
4502 if (VT == MVT::f32) { in getRecipEstimate()