38 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {  in getEquivalentMemType()
47 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {  in numBitsUnsigned()
53 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {  in numBitsSigned()
61 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,  in AMDGPUTargetLowering()  function in AMDGPUTargetLowering
615 bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {  in mayIgnoreSignedZero()
709 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,  in allUsesHaveSourceMods()
733 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,  in getTypeForExtReturn()
744 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {  in getVectorIdxTy()
748 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {  in isSelectSupported()
754 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()
762 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {  in ShouldShrinkFPConstant()
767 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,  in shouldReduceLoadWidth()
806 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,  in isLoadBitCastBeneficial()
831 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
835 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
839 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {  in isSDNodeAlwaysUniform()
862 SDValue AMDGPUTargetLowering::getNegatedExpression(  in getNegatedExpression()
886 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {  in isFAbsFree()
894 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {  in isFNegFree()
901 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,  in storeOfVectorConstantIsCheap()
907 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {  in aggressivelyPreferBuildVectorSources()
919 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {  in isTruncateFree()
928 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {  in isTruncateFree()
940 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {  in isZExtFree()
950 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {  in isZExtFree()
962 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
966 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
1055 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(  in analyzeFormalArgumentsCompute()
1172 SDValue AMDGPUTargetLowering::LowerReturn(  in LowerReturn()
1189 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,  in CCAssignFnForCall()
1194 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,  in CCAssignFnForReturn()
1199 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,  in addTokenForArgument()
1235 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,  in lowerUnhandledCall()
1262 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
1267 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
1278 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
1320 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
1337 bool AMDGPUTargetLowering::hasDefinedInitializer(const GlobalValue *GV) {  in hasDefinedInitializer()
1345 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,  in LowerGlobalAddress()
1394 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,  in LowerCONCAT_VECTORS()
1414 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
1435 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,  in combineFMinMaxLegacy()
1509 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {  in split64BitValue()
1523 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {  in getLoHalf64()
1531 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {  in getHiHalf64()
1543 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {  in getSplitDestVTs()
1558 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,  in splitVector()
1573 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,  in SplitVectorLoad()
1633 SDValue AMDGPUTargetLowering::WidenOrSplitVectorLoad(SDValue Op,  in WidenOrSplitVectorLoad()
1667 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,  in SplitVectorStore()
1711 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,  in LowerDIVREM24()
1822 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,  in LowerUDIVREM64()
2037 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,  in LowerUDIVREM()
2092 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,  in LowerSDIVREM()
2153 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {  in LowerFREM()
2167 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {  in LowerFCEIL()
2207 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {  in LowerFTRUNC()
2256 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFRINT()
2283 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFNEARBYINT()
2295 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND()
2324 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {  in LowerFFLOOR()
2349 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,  in LowerFLOG()
2362 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {  in lowerFEXP()
2380 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {  in LowerCTLZ_CTTZ()
2454 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP32()
2539 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP64()
2562 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,  in LowerUINT_TO_FP()
2599 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,  in LowerSINT_TO_FP()
2639 SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,  in LowerFP_TO_INT64()
2712 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_TO_FP16()
2811 SDValue AMDGPUTargetLowering::LowerFP_TO_INT(SDValue Op,  in LowerFP_TO_INT()
2846 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,  in LowerSIGN_EXTEND_INREG()
2874   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;  in isU24()
2881     AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;  in isI24()
2944 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {  in shouldCombineMemoryType()
2965 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,  in performLoadCombine()
3019 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,  in performStoreCombine()
3076 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,  in performAssertSZExtCombine()
3099 SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(  in performIntrinsicWOChainCombine()
3123 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(  in splitBinaryBitConstantOpImpl()
3146 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,  in performShlCombine()
3214 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,  in performSraCombine()
3249 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,  in performSrlCombine()
3298 SDValue AMDGPUTargetLowering::performTruncateCombine(  in performTruncateCombine()
3403 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,  in performMulCombine()
3457 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,  in performMulhsCombine()
3490 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,  in performMulhuCombine()
3529 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,  in getFFBX_U32()
3556 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,  in performCtlz_CttzCombine()
3673 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,  in performSelectCombine()
3731 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {  in isConstantCostlierToNegate()
3762 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,  in performFNegCombine()
3972 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,  in performFAbsCombine()
3997 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,  in performRcpCombine()
4009 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
4217 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
4253 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,  in loadStackInputValue()
4269 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,  in storeStackInputValue()
4288 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,  in loadInputValue()
4309 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(  in getImplicitParameterOffset()
4329 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
4479 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,  in getSqrtEstimate()
4497 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,  in getRecipEstimate()
4518 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
4660 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()
4701 unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(  in computeNumSignBitsForTargetInstr()
4724 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,  in isKnownNeverNaNForTargetNode()
4838 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {  in shouldExpandAtomicRMWInIR()
4849 bool AMDGPUTargetLowering::isConstantUnsignedBitfieldExtactLegal(  in isConstantUnsignedBitfieldExtactLegal()