76   Module *Mod = nullptr;  member in __anonb3ed75c90111::AMDGPUCodeGenPrepare
308   const DataLayout &DL = Mod->getDataLayout();  in canWidenScalarExtLoad()
430       Intrinsic::getDeclaration(Mod, Intrinsic::bitreverse, { I32Ty });  in promoteUniformBitreverseToI32()
528   FunctionCallee Intrin = Intrinsic::getDeclaration(Mod, IntrID);  in replaceMulWithMul24()
642                               Module *Mod) {  in optimizeWithRcp()  argument
652           Mod, Intrinsic::amdgcn_rcp, Ty);  in optimizeWithRcp()
671           Mod, Intrinsic::amdgcn_rcp, Ty);  in optimizeWithRcp()
682       Mod, Intrinsic::amdgcn_rcp, Ty);  in optimizeWithRcp()
701                                    Module *Mod) {  in optimizeWithFDivFast()  argument
721   Function *Decl = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_fdiv_fast);  in optimizeWithFDivFast()
784                                       RcpIsAccurate, Builder, Mod);  in visitFDiv()
787                                       HasFP32Denormals, Builder, Mod);  in visitFDiv()
796                               Builder, Mod);  in visitFDiv()
799                                      Builder, Mod);  in visitFDiv()
866   const DataLayout &DL = Mod->getDataLayout();  in getDivNumBits()
932   Function *RcpDecl = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp,  in expandDivRem24Impl()
1126   Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty);  in expandDivRem32()
1327                                MDNode::get(Mod->getContext(), LowAndHigh));  in visitLoadInst()
1331     int TySize = Mod->getDataLayout().getTypeSizeInBits(I.getType());  in visitLoadInst()
1383   Mod = &M;  in doInitialization()
1384   DL = &Mod->getDataLayout();  in doInitialization()