224   void assignValueToAddress(const CallLowering::ArgInfo &Arg,  in assignValueToAddress()
291   SmallVector<ArgInfo, 8> SplitRetInfos;  in lowerReturnVal()
296     ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx), 0);  in lowerReturnVal()
400 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,  in lowerParameter()
410   SmallVector<ArgInfo, 32> SplitArgs;  in lowerParameter()
415   for (ArgInfo &SplitArg : SplitArgs) {  in lowerParameter()
553       ArgInfo OrigArg(VRegs[i], Arg, i);  in lowerFormalArgumentsKernel()
608   SmallVector<ArgInfo, 32> SplitArgs;  in lowerFormalArguments()
653     ArgInfo OrigArg(VRegs[Idx], Arg, Idx);  in lowerFormalArguments()
932     SmallVectorImpl<ArgInfo> &InArgs) const {  in doCallerAndCalleePassArgsTheSameWay()
974     SmallVectorImpl<ArgInfo> &OutArgs) const {  in areCalleeOutgoingArgsTailCallable()
1031     SmallVectorImpl<ArgInfo> &InArgs, SmallVectorImpl<ArgInfo> &OutArgs) const {  in isEligibleForTailCallOptimization()
1105     SmallVectorImpl<ArgInfo> &OutArgs) const {  in lowerTailCall()
1263   SmallVector<ArgInfo, 8> OutArgs;  in lowerCall()
1267   SmallVector<ArgInfo, 8> InArgs;  in lowerCall()