Lines Matching refs:LSL
1285 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
1338 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1385 ET == AArch64_AM::LSL) && in isExtend()
1404 ET == AArch64_AM::LSL) && in isExtendLSL64()
1412 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1433 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1444 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
1455 if (ST != AArch64_AM::LSL) in isMovImm32Shifter()
1467 if (ST != AArch64_AM::LSL) in isMovImm64Shifter()
1479 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecShifter()
1489 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecHalfWordShifter()
1901 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
1909 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
1984 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateReg()
2003 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateVectorReg()
3202 .Case("lsl", AArch64_AM::LSL) in tryParseOptionalShiftExtend()
3226 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
4403 Operands.push_back(AArch64Operand::CreateShiftExtend(AArch64_AM::LSL, in parseOperand()