Lines Matching refs:constrainRegClass
701 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
707 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
747 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
751 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
755 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
758 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
786 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
787 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
1217 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
3691 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
3701 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
3845 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
3855 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
4159 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
4163 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
5093 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
5095 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
5097 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
5099 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
5233 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
5235 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
5237 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
5239 MRI.constrainRegClass(VR, RC); in genMaddR()