Lines Matching refs:SrcReg0
3643 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
3646 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
3652 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
5076 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
5094 if (Register::isVirtualRegister(SrcReg0)) in genFusedMultiply()
5095 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
5104 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
5110 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
5116 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
5227 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
5234 if (Register::isVirtualRegister(SrcReg0)) in genMaddR()
5235 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
5243 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()