Lines Matching refs:GPR32RegClass
379 : &AArch64::GPR32RegClass; in materializeInt()
411 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
469 ResultReg = createResultReg(&AArch64::GPR32RegClass); in materializeGV()
1301 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1344 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1387 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1429 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1711 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1817 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1822 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1827 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
2526 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2545 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2566 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2644 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2666 RC = &AArch64::GPR32RegClass; in selectSelect()
2829 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2958 RC = &AArch64::GPR32RegClass; in fastLowerArguments()
3741 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass, in fastLowerIntrinsicCall()
3915 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
3953 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg, in emiti1Ext()
3972 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
4006 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
4031 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_ri()
4108 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4134 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_ri()
4224 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4250 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_ri()
4372 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitIntExt()
4555 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in selectRem()
4744 case MVT::i32: RC = &AArch64::GPR32RegClass; break; in selectBitCast()
4841 RC = &AArch64::GPR32RegClass; in selectSDiv()
4975 ResRC = &AArch64::GPR32RegClass; in selectAtomicCmpXchg()
4994 const unsigned ResultReg2 = createResultReg(&AArch64::GPR32RegClass); in selectAtomicCmpXchg()
4995 const unsigned ScratchReg = createResultReg(&AArch64::GPR32RegClass); in selectAtomicCmpXchg()