Lines Matching refs:WS
27 WriteRef::WriteRef(unsigned SourceIndex, WriteState *WS) in WriteRef() argument
29 Write(WS) {} in WriteRef()
107 for (WriteState &WS : IS->getDefs()) { in onInstructionExecuted()
108 if (WS.isEliminated()) in onInstructionExecuted()
111 MCPhysReg RegID = WS.getRegisterID(); in onInstructionExecuted()
118 assert(WS.getCyclesLeft() != UNKNOWN_CYCLES && in onInstructionExecuted()
120 assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!"); in onInstructionExecuted()
127 if (WR.getWriteState() == &WS) in onInstructionExecuted()
132 if (OtherWR.getWriteState() == &WS) in onInstructionExecuted()
136 if (!WS.clearsSuperRegisters()) in onInstructionExecuted()
141 if (OtherWR.getWriteState() == &WS) in onInstructionExecuted()
230 WriteState &WS = *Write.getWriteState(); in addRegisterWrite() local
231 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite()
256 bool IsWriteZero = WS.isWriteZero(); in addRegisterWrite()
257 bool IsEliminated = WS.isEliminated(); in addRegisterWrite()
260 WS.setPRF(RRI.IndexPlusCost.first); in addRegisterWrite()
266 if (!WS.clearsSuperRegisters()) { in addRegisterWrite()
276 OtherWS->addUser(OtherWrite.getSourceIndex(), &WS); in addRegisterWrite()
283 WS.clearsSuperRegisters() ? RegID : WS.getRegisterID(); in addRegisterWrite()
306 if (!WS.clearsSuperRegisters()) in addRegisterWrite()
320 const WriteState &WS, MutableArrayRef<unsigned> FreedPhysRegs) { in removeRegisterWrite() argument
323 if (WS.isEliminated()) in removeRegisterWrite()
326 MCPhysReg RegID = WS.getRegisterID(); in removeRegisterWrite()
333 assert(WS.getCyclesLeft() != UNKNOWN_CYCLES && in removeRegisterWrite()
335 assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!"); in removeRegisterWrite()
337 bool ShouldFreePhysRegs = !WS.isWriteZero(); in removeRegisterWrite()
342 if (!WS.clearsSuperRegisters()) { in removeRegisterWrite()
352 if (WR.getWriteState() == &WS) in removeRegisterWrite()
357 if (OtherWR.getWriteState() == &WS) in removeRegisterWrite()
361 if (!WS.clearsSuperRegisters()) in removeRegisterWrite()
366 if (OtherWR.getWriteState() == &WS) in removeRegisterWrite()
371 bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS, in canEliminateMove() argument
374 const RegisterMapping &RMTo = RegisterMappings[WS.getRegisterID()]; in canEliminateMove()
405 if (RRITo.RenameAs && RRITo.RenameAs != WS.getRegisterID()) in canEliminateMove()
406 if (!WS.clearsSuperRegisters()) in canEliminateMove()
438 const WriteState &WS = Writes[E - (I + 1)]; in tryEliminateMoveOrSwap() local
439 if (!canEliminateMove(WS, RS, RegisterFileIndex)) in tryEliminateMoveOrSwap()
445 WriteState &WS = Writes[E - (I + 1)]; in tryEliminateMoveOrSwap() local
448 const RegisterMapping &RMTo = RegisterMappings[WS.getRegisterID()]; in tryEliminateMoveOrSwap()
455 MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID(); in tryEliminateMoveOrSwap()
466 WS.setWriteZero(); in tryEliminateMoveOrSwap()
470 WS.setEliminated(); in tryEliminateMoveOrSwap()
546 const WriteState &WS = *WR.getWriteState(); in collectWrites()
548 << MRI.getName(WS.getRegisterID()) << " (defined by instruction #" in collectWrites()
567 const WriteState *WS = WR.getWriteState(); in checkRAWHazards() local
568 unsigned WriteResID = WS->getWriteResourceID(); in checkRAWHazards()
571 if (WS->getCyclesLeft() == UNKNOWN_CYCLES) { in checkRAWHazards()
580 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRAWHazards()
629 WriteState &WS = *WR.getWriteState(); in addRegisterRead() local
631 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()