125   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131   bool isProfitableToConv3Addr(Register RegA, Register RegB);
135                           Register RegB, unsigned Dist);
416 static bool regsAreCompatible(Register RegA, Register RegB,  in regsAreCompatible()  argument
418   if (RegA == RegB)  in regsAreCompatible()
420   if (!RegA || !RegB)  in regsAreCompatible()
422   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
438                                                       Register RegB,  in isProfitableToCommute()  argument
478     MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);  in isProfitableToCommute()
506   if (!noUseAfterLastDef(RegB, Dist, LastDefB))  in isProfitableToCommute()
527   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
574                                                         Register RegB) {  in isProfitableToConv3Addr()  argument
581   MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);  in isProfitableToConv3Addr()
592     Register RegA, Register RegB, unsigned Dist) {  in convertInstTo3Addr()  argument
633   DstRegMap.erase(RegB);  in convertInstTo3Addr()
1373   Register RegB = 0;  in processTiedPairs()  local
1384     RegB = MI->getOperand(SrcIdx).getReg();  in processTiedPairs()
1387     if (RegA == RegB) {  in processTiedPairs()
1396     assert(RegB.isVirtual() && "cannot make instruction into two-address form");  in processTiedPairs()
1413     MIB.addReg(RegB, 0, SubRegB);  in processTiedPairs()
1414     const TargetRegisterClass *RC = MRI->getRegClass(RegB);  in processTiedPairs()
1423         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1449     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&  in processTiedPairs()
1457     if (RegA.isVirtual() && RegB.isVirtual())  in processTiedPairs()
1466     SrcRegMap[RegA] = RegB;  in processTiedPairs()
1474         if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {  in processTiedPairs()
1491         LV && LV->getVarInfo(RegB).removeKill(*MI)) {  in processTiedPairs()
1494       LV->addVirtualRegisterKilled(RegB, *PrevMI);  in processTiedPairs()
1499       LiveInterval &LI = LIS->getInterval(RegB);  in processTiedPairs()
1514       if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {  in processTiedPairs()