43 TargetInstrInfo::~TargetInstrInfo() {  in ~TargetInstrInfo()
47 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,  in getRegClass()
67 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
74 void TargetInstrInfo::insertNoops(MachineBasicBlock &MBB,  in insertNoops()
100 unsigned TargetInstrInfo::getInlineAsmLength(  in getInlineAsmLength()
141 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,  in ReplaceTailWithBranchTo()
167 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,  in commuteInstructionImpl()
250 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,  in commuteInstruction()
265 bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,  in fixCommutedOpIndices()
296 bool TargetInstrInfo::findCommutedOpIndices(const MachineInstr &MI,  in findCommutedOpIndices()
320 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {  in isUnpredicatedTerminator()
331 bool TargetInstrInfo::PredicateInstruction(  in PredicateInstruction()
361 bool TargetInstrInfo::hasLoadFromStackSlot(  in hasLoadFromStackSlot()
375 bool TargetInstrInfo::hasStoreToStackSlot(  in hasStoreToStackSlot()
389 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,  in getStackSlotRange()
419 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,  in reMaterialize()
429 bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,  in produceSameValue()
435 MachineInstr &TargetInstrInfo::duplicate(MachineBasicBlock &MBB,  in duplicate()
475 MCInst TargetInstrInfo::getNop() const { llvm_unreachable("Not implemented"); }  in getNop()
478 TargetInstrInfo::getPatchpointUnfoldableRange(const MachineInstr &MI) const {  in getPatchpointUnfoldableRange()
497                                     const TargetInstrInfo &TII) {  in foldPatchpoint()
560 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,  in foldMemoryOperand()
652 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,  in foldMemoryOperand()
700 bool TargetInstrInfo::hasReassociableOperands(  in hasReassociableOperands()
719 bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,  in hasReassociableSibling()
749 bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,  in isReassociationCandidate()
777 bool TargetInstrInfo::getMachineCombinerPatterns(  in getMachineCombinerPatterns()
801 TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {  in isThroughputPattern()
807 void TargetInstrInfo::reassociateOps(  in reassociateOps()
815   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();  in reassociateOps()
891 void TargetInstrInfo::genAlternativeCodeSequence(  in genAlternativeCodeSequence()
918 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(  in isReallyTriviallyReMaterializableGeneric()
998 int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {  in getSPAdjust()
1022 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
1045 bool TargetInstrInfo::usePreRAHazardRecognizer() const {  in usePreRAHazardRecognizer()
1050 ScheduleHazardRecognizer *TargetInstrInfo::
1058 ScheduleHazardRecognizer *TargetInstrInfo::CreateTargetMIHazardRecognizer(  in CreateTargetMIHazardRecognizer()
1064 ScheduleHazardRecognizer *TargetInstrInfo::
1071 bool TargetInstrInfo::getMemOperandWithOffset(  in getMemOperandWithOffset()
1089 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
1105 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
1120 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()
1136 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,  in defaultDefLatency()
1147 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {  in getPredicationCost()
1151 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
1162 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,  in hasLowDefLatency()
1175 TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,  in describeLoadedValue()
1257 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
1269 int TargetInstrInfo::computeDefOperandLatency(  in computeDefOperandLatency()
1283 bool TargetInstrInfo::getRegSequenceInputs(  in getRegSequenceInputs()
1310 bool TargetInstrInfo::getExtractSubregInputs(  in getExtractSubregInputs()
1335 bool TargetInstrInfo::getInsertSubregInputs(  in getInsertSubregInputs()
1364 std::string TargetInstrInfo::createMIROperandComment(  in createMIROperandComment()
1419 TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() {}  in ~PipelinerLoopInfo()