1090                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
1100     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
1102   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1164                                        unsigned DefIdx) const {  in hasLowDefLatency()
1170   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1259                                        unsigned DefIdx,  in getOperandLatency()  argument
1264   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1284     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1290     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1294   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1311     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1317     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1321   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1336     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1342     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1346   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()