Lines Matching refs:IntvOut
1607 unsigned IntvOut, SlotIndex EnterAfter){ in splitLiveThroughBlock() argument
1613 << ", live-through " << IntvIn << " -> " << IntvOut); in splitLiveThroughBlock()
1615 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks"); in splitLiveThroughBlock()
1623 if (!IntvOut) { in splitLiveThroughBlock()
1644 selectIntv(IntvOut); in splitLiveThroughBlock()
1651 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) { in splitLiveThroughBlock()
1657 selectIntv(IntvOut); in splitLiveThroughBlock()
1664 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf"); in splitLiveThroughBlock()
1666 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter || in splitLiveThroughBlock()
1674 selectIntv(IntvOut); in splitLiveThroughBlock()
1697 selectIntv(IntvOut); in splitLiveThroughBlock()
1802 unsigned IntvOut, SlotIndex EnterAfter) { in splitRegOutBlock() argument
1808 << BI.LastInstr << ", reg-out " << IntvOut in splitRegOutBlock()
1814 assert(IntvOut && "Must have register out"); in splitRegOutBlock()
1825 selectIntv(IntvOut); in splitRegOutBlock()
1837 selectIntv(IntvOut); in splitRegOutBlock()
1853 selectIntv(IntvOut); in splitRegOutBlock()