Lines Matching refs:LegalOps
1784 if (DemandedBits.isOneValue() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
2761 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
6010 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
6059 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6089 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6110 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
6117 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6125 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6173 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6181 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6218 getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); in getNegatedExpression()
6229 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6237 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6264 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, in getNegatedExpression()
6269 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, in getNegatedExpression()