Lines Matching refs:RegVT
2775 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2776 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2814 MVT VT = BB.RegVT; in visitBitTestCase()
8291 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in GetRegistersForValue() local
8293 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in GetRegistersForValue()
8307 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in GetRegistersForValue()
8313 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in GetRegistersForValue()
8314 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
8318 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
8335 ValueVT = RegVT; in GetRegistersForValue()
8340 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT, RegVT); in GetRegistersForValue()
8364 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in GetRegistersForValue()
8679 MVT RegVT = R->getSimpleValueType(0); in visitInlineAsm() local
8682 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) in visitInlineAsm()
8688 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); in visitInlineAsm()
10254 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments() local
10256 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, in LowerArguments()
10262 RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()