Lines Matching refs:Preds
556 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
839 for (SDep &Pred : SU->Preds) { in UnscheduleNodeBottomUp()
1062 for (SDep &Pred : SU->Preds) { in TryUnfoldSU()
1187 for (SDep &Pred : SU->Preds) in CopyAndMoveSuccessors()
1355 for (SDep &Pred : SU->Preds) { in DelayForLiveRegsBottomUp()
1963 for (unsigned P = Temp.PredsProcessed; P < TempSU->Preds.size(); ++P) { in CalcNodeSethiUllmanNumber()
1964 auto &Pred = TempSU->Preds[P]; in CalcNodeSethiUllmanNumber()
1987 for (const SDep &Pred : TempSU->Preds) { in CalcNodeSethiUllmanNumber()
2090 for (const SDep &Pred : SU->Preds) { in HighRegPressure()
2139 for (const SDep &Pred : SU->Preds) { in RegPressureDiff()
2182 for (const SDep &Pred : SU->Preds) { in scheduledNode()
2264 for (const SDep &Pred : SU->Preds) { in unscheduledNode()
2350 for (const SDep &Pred : SU->Preds) { in calcMaxScratches()
2361 for (const SDep &Pred : SU->Preds) { in hasOnlyLiveInOpers()
2420 for (const SDep &Pred : SU->Preds) { in initVRegCycle()
2432 for (const SDep &Pred : SU->Preds) { in resetVRegCycle()
2450 for (const SDep &Pred : SU->Preds) { in hasVRegCycleUse()
2852 for (const SDep &SuccPred : SuccSU->Preds) { in canClobberReachingPhysRegUse()
2963 for (const SDep &Pred : SU.Preds) in PrescheduleNodesWithMultipleUses()
2987 for (const SDep &Pred : SU.Preds) in PrescheduleNodesWithMultipleUses()