162   for (SDep &Pred : SU->Preds) {  in ReleasePredecessors()
163     ReleasePred(SU, &Pred);  in ReleasePredecessors()
164     if (Pred.isAssignedRegDep()) {  in ReleasePredecessors()
169       if (!LiveRegDefs[Pred.getReg()]) {  in ReleasePredecessors()
171         LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
172         LiveRegCycles[Pred.getReg()] = CurCycle;  in ReleasePredecessors()
282     for (SDep &Pred : SU->Preds) {  in CopyAndMoveSuccessors()
283       if (Pred.isCtrl())  in CopyAndMoveSuccessors()
284         ChainPred = Pred;  in CopyAndMoveSuccessors()
285       else if (Pred.getSUnit()->getNode() &&  in CopyAndMoveSuccessors()
286                Pred.getSUnit()->getNode()->isOperandOf(LoadNode))  in CopyAndMoveSuccessors()
287         LoadPreds.push_back(Pred);  in CopyAndMoveSuccessors()
289         NodePreds.push_back(Pred);  in CopyAndMoveSuccessors()
304       const SDep &Pred = LoadPreds[i];  in CopyAndMoveSuccessors()  local
305       RemovePred(SU, Pred);  in CopyAndMoveSuccessors()
307         AddPred(LoadSU, Pred);  in CopyAndMoveSuccessors()
311       const SDep &Pred = NodePreds[i];  in CopyAndMoveSuccessors()  local
312       RemovePred(SU, Pred);  in CopyAndMoveSuccessors()
313       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
352   for (SDep &Pred : SU->Preds)  in CopyAndMoveSuccessors()
353     if (!Pred.isArtificial())  in CopyAndMoveSuccessors()
354       AddPred(NewSU, Pred);  in CopyAndMoveSuccessors()
474   for (SDep &Pred : SU->Preds) {  in DelayForLiveRegsBottomUp()
475     if (Pred.isAssignedRegDep()) {  in DelayForLiveRegsBottomUp()
476       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs,  in DelayForLiveRegsBottomUp()