Lines Matching refs:SrcVT
725 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
726 TypeSize SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
730 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
738 (SrcVT != MVT::i1 || in LegalizeLoadOps()
743 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
763 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
768 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
774 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
851 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
879 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
882 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps()
883 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT? in LegalizeLoadOps()
884 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
888 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
891 SrcVT, LD->getMemOperand()); in LegalizeLoadOps()
893 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType); in LegalizeLoadOps()
903 if (SrcVT.getScalarType() == MVT::f16) { in LegalizeLoadOps()
904 EVT ISrcVT = SrcVT.changeTypeToInteger(); in LegalizeLoadOps()
916 assert(!SrcVT.isVector() && in LegalizeLoadOps()
929 Chain, Ptr, SrcVT, in LegalizeLoadOps()
935 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
937 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); in LegalizeLoadOps()
2289 EVT SrcVT = Op0.getValueType(); in ExpandLegalINT_TO_FP() local
2293 if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64) && in ExpandLegalINT_TO_FP()
2364 if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) || in ExpandLegalINT_TO_FP()
2365 (SrcVT == MVT::i64 && DestVT == MVT::f64)) { in ExpandLegalINT_TO_FP()
2381 EVT SetCCVT = getSetCCResultType(SrcVT); in ExpandLegalINT_TO_FP()
2384 dl, SetCCVT, Op0, DAG.getConstant(0, dl, SrcVT), ISD::SETLT); in ExpandLegalINT_TO_FP()
2386 EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout()); in ExpandLegalINT_TO_FP()
2388 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst); in ExpandLegalINT_TO_FP()
2389 SDValue AndConst = DAG.getConstant(1, dl, SrcVT); in ExpandLegalINT_TO_FP()
2390 SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst); in ExpandLegalINT_TO_FP()
2391 SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr); in ExpandLegalINT_TO_FP()
2397 SDValue InCvt = DAG.getSelect(dl, SrcVT, SignBitTest, Or, Op0); in ExpandLegalINT_TO_FP()
2429 SrcVT.getSizeInBits() - 1 && in ExpandLegalINT_TO_FP()
2439 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0, in ExpandLegalINT_TO_FP()
2440 DAG.getConstant(0, dl, SrcVT), ISD::SETLT); in ExpandLegalINT_TO_FP()
2450 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()