Lines Matching refs:getSimpleVT
250 MVT VT = RealVT.getSimpleVT(); in getRegForValue()
254 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue()
313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
396 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); in getRegForGEPIndex()
399 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); in getRegForGEPIndex()
481 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(), in selectBinaryOp()
482 VT.getSimpleVT()); in selectBinaryOp()
513 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp()
514 VT.getSimpleVT()); in selectBinaryOp()
528 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp()
1396 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1423 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast()
1424 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast()
1464 MVT Ty = ETy.getSimpleVT(); in selectFreeze()
1623 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, in selectFNeg()
1638 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1644 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg()
1645 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1649 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
1668 MVT VT = RealVT.getSimpleVT(); in selectExtractValue()