Lines Matching refs:getOpcode
264 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
269 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
652 switch (StoreVal.getOpcode()) { in getStoreSource()
896 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
904 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
905 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
912 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
970 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
987 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
996 (LD->getOperand(2).getOpcode() != ISD::TargetConstant || in canSplitIdx()
1010 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) in reassociationCanBreakAddressingModePattern()
1062 if (N0.getOpcode() != Opc) in reassociateOpsCommutative()
1223 unsigned Opc = Op.getOpcode(); in PromoteOperand()
1290 unsigned Opc = Op.getOpcode(); in PromoteIntBinOp()
1358 unsigned Opc = Op.getOpcode(); in PromoteIntShiftOp()
1391 if (Op && Op.getOpcode() != ISD::DELETED_NODE) in PromoteIntShiftOp()
1407 unsigned Opc = Op.getOpcode(); in PromoteExtend()
1420 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); in PromoteExtend()
1438 unsigned Opc = Op.getOpcode(); in PromoteLoad()
1570 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1571 RV.getOpcode() != ISD::DELETED_NODE && in Run()
1589 if (RV.getOpcode() != ISD::EntryToken) { in Run()
1607 switch (N->getOpcode()) { in visit()
1752 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
1755 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
1756 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
1768 switch (N->getOpcode()) { in combine()
1797 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) && in combine()
1805 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, in combine()
1851 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) in visitTokenFactor()
1880 switch (Op.getOpcode()) { in visitTokenFactor()
1966 switch (CurNode->getOpcode()) { in visitTokenFactor()
2076 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
2085 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
2102 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && in foldBinOpIntoSelect()
2110 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { in foldBinOpIntoSelect()
2115 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) in foldBinOpIntoSelect()
2133 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect()
2171 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubBoolOfMaskedVal()
2177 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal()
2181 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2185 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
2193 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2212 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubOfSignBit()
2217 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit()
2221 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2291 if (N0.getOpcode() == ISD::SUB && in visitADDLike()
2300 if (N0.getOpcode() == ISD::SUB && in visitADDLike()
2312 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
2326 if (N0.getOpcode() == ISD::OR && in visitADDLike()
2346 if (N0.getOpcode() == ISD::OR && N0.hasOneUse() && in visitADDLike()
2361 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) in visitADDLike()
2365 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitADDLike()
2369 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) in visitADDLike()
2373 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) in visitADDLike()
2377 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2383 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2389 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2395 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2401 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && in visitADDLike()
2402 N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLike()
2404 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), in visitADDLike()
2408 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { in visitADDLike()
2421 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2442 if (N0.getOpcode() == ISD::ADD) { in visitADDLike()
2462 N0.getOpcode() == ISD::ADD) { in visitADDLike()
2470 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitADDLike()
2506 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2513 if ((N0.getOpcode() == ISD::ADD) && in visitADD()
2514 (N0.getOperand(1).getOpcode() == ISD::VSCALE) && in visitADD()
2515 (N1.getOpcode() == ISD::VSCALE)) { in visitADD()
2523 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitADD()
2524 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
2532 if ((N0.getOpcode() == ISD::ADD) && in visitADD()
2533 (N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR) && in visitADD()
2534 (N1.getOpcode() == ISD::STEP_VECTOR)) { in visitADD()
2546 unsigned Opcode = N->getOpcode(); in visitADDSAT()
2592 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
2597 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { in getAsCarry()
2610 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY && in getAsCarry()
2611 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) in getAsCarry()
2615 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) in getAsCarry()
2634 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) in foldAddSubMasked1()
2653 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLikeCommutative()
2668 N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) { in visitADDLikeCommutative()
2677 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitADDLikeCommutative()
2684 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitADDLikeCommutative()
2693 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
2701 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
2711 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
2769 if (V.getOpcode() != ISD::XOR) in extractBooleanFlip()
2802 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO()
2815 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitADDO()
2852 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
2882 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
2976 if (Carry1.getOpcode() != ISD::UADDO) in combineADDCARRYDiamond()
2985 if (Carry0.getOpcode() == ISD::ADDCARRY && in combineADDCARRYDiamond()
2988 } else if (Carry0.getOpcode() == ISD::UADDO && in combineADDCARRYDiamond()
3067 unsigned Opcode = Carry0.getOpcode(); in combineCarryDiamond()
3068 if (Opcode != Carry1.getOpcode()) in combineCarryDiamond()
3096 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND) in combineCarryDiamond()
3121 if (N->getOpcode() == ISD::AND) in combineCarryDiamond()
3142 if ((N0.getOpcode() == ISD::ADD || in visitADDCARRYLike()
3143 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitADDCARRYLike()
3196 if (N->getOpcode() != ISD::SUB || in foldSubToUSubSat()
3206 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in foldSubToUSubSat()
3215 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3225 if (Op1.getOpcode() == ISD::TRUNCATE && in foldSubToUSubSat()
3226 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
3230 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) in foldSubToUSubSat()
3233 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) in foldSubToUSubSat()
3294 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3297 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3319 if (N1->getOpcode() == ISD::ABS && in visitSUB()
3327 if (N1S && N1S.getOpcode() == ISD::SUB && in visitSUB()
3341 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitSUB()
3345 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
3349 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
3353 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
3357 if (N0.getOpcode() == ISD::ADD && in visitSUB()
3367 if (N1.getOpcode() == ISD::ADD) { in visitSUB()
3378 if (N0.getOpcode() == ISD::SUB && in visitSUB()
3388 if (N0.getOpcode() == ISD::SUB && in visitSUB()
3398 if (N0.getOpcode() == ISD::ADD && in visitSUB()
3399 (N0.getOperand(1).getOpcode() == ISD::SUB || in visitSUB()
3400 N0.getOperand(1).getOpcode() == ISD::ADD) && in visitSUB()
3402 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), in visitSUB()
3406 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && in visitSUB()
3412 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3418 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) in visitSUB()
3424 if (N1.getOpcode() == ISD::AND) { in visitSUB()
3438 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { in visitSUB()
3439 if (N1.getOperand(0).getOpcode() == ISD::SUB && in visitSUB()
3446 if (N1.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3474 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) { in visitSUB()
3491 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD && in visitSUB()
3497 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD && in visitSUB()
3504 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitSUB()
3510 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitSUB()
3519 if (N1.getOpcode() == ISD::ZERO_EXTEND && in visitSUB()
3529 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
3543 if (N1C && GA->getOpcode() == ISD::GlobalAddress) in visitSUB()
3555 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
3565 if (N1.getOpcode() == ISD::VSCALE) { in visitSUB()
3571 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { in visitSUB()
3579 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
3628 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1})) in visitSUBSAT()
3670 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
3711 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
3762 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); in visitMULFIX()
3902 if (N0.getOpcode() == ISD::SHL && in visitMUL()
3916 if (N0.getOpcode() == ISD::SHL && in visitMUL()
3920 } else if (N1.getOpcode() == ISD::SHL && in visitMUL()
3934 N0.getOpcode() == ISD::ADD && in visitMUL()
3944 if (N0.getOpcode() == ISD::VSCALE) in visitMUL()
3953 if (N0.getOpcode() == ISD::STEP_VECTOR) in visitMUL()
3978 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); in visitMUL()
4022 unsigned Opcode = Node->getOpcode(); in useDivRem()
4058 if (User == Node || User->getOpcode() == ISD::DELETED_NODE || in useDivRem()
4064 unsigned UserOpc = User->getOpcode(); in useDivRem()
4094 unsigned Opc = N->getOpcode(); in simplifyDivRem()
4351 if (N1.getOpcode() == ISD::SHL) { in visitUDIVLike()
4379 unsigned Opcode = N->getOpcode(); in visitREM()
4417 if (N1.getOpcode() == ISD::SHL && in visitREM()
4605 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
4615 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
4700 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
4723 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitMULO()
4770 unsigned Opcode = N->getOpcode(); in visitIMINMAX()
4784 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitIMINMAX()
4815 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands()
4816 unsigned HandOpcode = N0.getOpcode(); in hoistLogicOpWithSameOpcodeHands()
4819 assert(HandOpcode == N1.getOpcode() && "Bad input!"); in hoistLogicOpWithSameOpcodeHands()
5137 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
5172 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitANDLike()
5359 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && in SearchForAndLoads()
5368 switch(Op.getOpcode()) { in SearchForAndLoads()
5392 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
5465 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
5489 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
5509 assert(N->getOpcode() == ISD::AND); in unfoldExtremeBitClearingToShifts()
5525 OuterShift = M->getOpcode(); in unfoldExtremeBitClearingToShifts()
5561 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); in combineShiftAnd1ToBitTest()
5572 if (Not.getOpcode() == ISD::ANY_EXTEND) in combineShiftAnd1ToBitTest()
5581 if (Srl.getOpcode() == ISD::TRUNCATE) in combineShiftAnd1ToBitTest()
5585 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() || in combineShiftAnd1ToBitTest()
5705 if (N0.getOpcode() == ISD::OR && in visitAND()
5709 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
5734 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
5736 N0.getOperand(0).getOpcode() == ISD::LOAD && in visitAND()
5738 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
5739 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? in visitAND()
5857 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD || in visitAND()
5858 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
5859 N0.getOperand(0).getOpcode() == ISD::LOAD))) { in visitAND()
5861 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND in visitAND()
5882 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
5893 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { in visitAND()
5896 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
5899 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && in visitAND()
5935 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { in visitAND()
5955 if (LHS->getOpcode() != ISD::SIGN_EXTEND) in visitAND()
5991 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
5993 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
5995 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6008 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6018 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6020 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
6034 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6045 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6099 unsigned Opc = N.getOpcode(); in isBSwapHWordElement()
6104 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement()
6181 if (N.getOpcode() == ISD::OR) in isBSwapHWordPair()
6185 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
6203 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && in matchBSwapHWordOrAndAnd()
6207 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) in matchBSwapHWordOrAndAnd()
6221 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6274 } else if (N0.getOpcode() == ISD::OR) { in MatchBSwapHWord()
6320 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in visitORLike()
6346 if (N0.getOpcode() == ISD::AND && in visitORLike()
6347 N1.getOpcode() == ISD::AND && in visitORLike()
6363 if (N0.getOpcode() == ISD::AND) { in visitORCommutative()
6514 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && in visitOR()
6530 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
6555 if (Op.getOpcode() == ISD::AND && in stripConstantMask()
6567 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
6603 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && in extractShiftForRotate()
6617 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
6618 ExtractFrom.getOpcode() == ISD::ADD && in extractShiftForRotate()
6634 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; in extractShiftForRotate()
6635 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) in extractShiftForRotate()
6642 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
6643 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
6648 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
6754 if (IsRotate && Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) { in matchRotateSub()
6767 if (Neg.getOpcode() != ISD::SUB) in matchRotateSub()
6776 if (MaskLoBits && Pos.getOpcode() == ISD::AND) { in matchRotateSub()
6800 (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) in matchRotateSub()
6812 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { in matchRotateSub()
6885 if (Op.getOpcode() != BinOpc) in MatchFunnelPosNeg()
6912 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && in MatchFunnelPosNeg()
6942 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
6988 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
6996 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
7056 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
7057 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7058 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
7059 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
7060 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
7061 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7062 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
7063 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
7159 switch (Op.getOpcode()) { in calculateByteProvider()
7199 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
7261 switch (Value.getOpcode()) { in stripTruncAndExt()
7346 if (Trunc.getOpcode() != ISD::TRUNCATE) in mergeTruncStores()
7352 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
7501 assert(N->getOpcode() == ISD::OR && in MatchLoadCombine()
7681 assert(N->getOpcode() == ISD::XOR); in unfoldMaskedMerge()
7693 if (And.getOpcode() != ISD::AND || !And.hasOneUse()) in unfoldMaskedMerge()
7696 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) in unfoldMaskedMerge()
7798 unsigned N0Opcode = N0.getOpcode(); in visitXOR()
7872 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && in visitXOR()
7879 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && in visitXOR()
7919 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { in visitXOR()
7958 if (N0Opcode == N1.getOpcode()) in visitXOR()
7986 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
7992 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic()
7999 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic()
8072 switch (LHS.getOpcode()) { in visitShiftByConstant()
8080 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
8094 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || in visitShiftByConstant()
8095 BinOpLHSVal.getOpcode() == ISD::SRA || in visitShiftByConstant()
8096 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
8098 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
8099 BinOpLHSVal.getOpcode() == ISD::SELECT; in visitShiftByConstant()
8110 SDValue NewRHS = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(1), in visitShiftByConstant()
8114 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant()
8116 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
8120 assert(N->getOpcode() == ISD::TRUNCATE); in distributeTruncateThroughAnd()
8121 assert(N->getOperand(0).getOpcode() == ISD::AND); in distributeTruncateThroughAnd()
8171 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); in visitRotate()
8185 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
8186 N1.getOperand(0).getOpcode() == ISD::AND) { in visitRotate()
8188 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); in visitRotate()
8191 unsigned NextOp = N0.getOpcode(); in visitRotate()
8198 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()
8205 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), in visitRotate()
8232 if (N0.getOpcode() == ISD::AND) { in visitSHL()
8237 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
8263 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
8264 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSHL()
8273 if (N0.getOpcode() == ISD::SHL) { in visitSHL()
8303 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
8304 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
8305 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
8306 N0.getOperand(0).getOpcode() == ISD::SHL) { in visitSHL()
8337 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); in visitSHL()
8347 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
8348 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
8373 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) && in visitSHL()
8382 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), in visitSHL()
8393 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && in visitSHL()
8420 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && in visitSHL()
8432 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && in visitSHL()
8441 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1); in visitSHL()
8445 if (N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse() && in visitSHL()
8458 if (N0.getOpcode() == ISD::VSCALE) in visitSHL()
8467 if (N0.getOpcode() == ISD::STEP_VECTOR) in visitSHL()
8485 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
8498 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
8504 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH()
8505 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; in combineShiftToMULH()
8507 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
8545 return (N->getOpcode() == ISD::SRA ? DAG.getSExtOrTrunc(Result, DL, WideVT1) in combineShiftToMULH()
8580 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { in visitSRA()
8599 if (N0.getOpcode() == ISD::SRA) { in visitSRA()
8617 if (N1.getOpcode() == ISD::BUILD_VECTOR) in visitSRA()
8619 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
8635 if (N0.getOpcode() == ISD::SHL && N1C) { in visitSRA()
8673 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && N1C && in visitSRA()
8674 N0.getOperand(0).getOpcode() == ISD::SHL && in visitSRA()
8703 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
8704 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRA()
8713 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
8714 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
8715 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
8782 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
8808 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
8809 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
8848 if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && in visitSRL()
8859 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
8885 if (N0.getOpcode() == ISD::SRA) in visitSRL()
8890 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
8927 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
8928 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRL()
8965 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
8967 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { in visitSRL()
8970 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
8988 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
9009 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, in visitFunnelShift()
9105 if (AbsOp1.getOpcode() != ISD::SUB) in combineABSToABD()
9111 unsigned Opc0 = Op0.getOpcode(); in combineABSToABD()
9113 if (Opc0 != Op1.getOpcode() || in combineABSToABD()
9139 if (N0.getOpcode() == ISD::ABS) in visitABS()
9159 if (N0.getOpcode() == ISD::BSWAP) in visitBSWAP()
9172 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
9312 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
9448 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
9516 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { in visitSELECT()
9529 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { in visitSELECT()
9543 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { in visitSELECT()
9562 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { in visitSELECT()
9589 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
9609 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { in visitSELECT()
9663 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
9664 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
9665 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
9710 if (!isNullConstant(BasePtr) || Index.getOpcode() != ISD::ADD) in refineUniformBase()
9729 if (Index.getOpcode() == ISD::ZERO_EXTEND) { in refineIndexType()
9738 if (Index.getOpcode() == ISD::SIGN_EXTEND) { in refineIndexType()
9952 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
9960 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) in visitVSELECT()
9963 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) in visitVSELECT()
10004 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && in visitVSELECT()
10034 if (Other && Other.getOpcode() == ISD::ADD) { in visitVSELECT()
10051 if (OpRHS.getOpcode() == CondRHS.getOpcode() && in visitVSELECT()
10052 (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
10053 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
10085 if (Other.getOpcode() == ISD::SUB && in visitVSELECT()
10086 LHS.getOpcode() == ISD::ZERO_EXTEND && LHS.getOperand(0) == OpLHS && in visitVSELECT()
10087 OpRHS.getOpcode() == ISD::TRUNCATE && OpRHS.getOperand(0) == RHS) { in visitVSELECT()
10103 Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) in visitVSELECT()
10106 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
10107 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
10108 if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
10109 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
10118 if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && in visitVSELECT()
10132 if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && in visitVSELECT()
10161 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
10162 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
10200 } else if (SCC.getOpcode() == ISD::SETCC) { in visitSELECT_CC()
10223 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; in visitSETCC()
10261 if (N0->getOpcode() == ISD::FREEZE && N0.hasOneUse() && N1C) { in visitSETCC()
10267 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse() && N0C) { in visitSETCC()
10287 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { in visitSETCC()
10350 unsigned Opcode = N->getOpcode(); in tryToFoldExtendSelectLoad()
10359 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
10393 unsigned Opcode = N->getOpcode(); in tryToFoldExtendOfConstant()
10412 if (N0->getOpcode() == ISD::SELECT) { in tryToFoldExtendOfConstant()
10493 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
10516 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
10525 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
10565 assert((N->getOpcode() == ISD::SIGN_EXTEND || in CombineExtLoad()
10566 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
10586 if (N0->getOpcode() != ISD::LOAD) in CombineExtLoad()
10598 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) in CombineExtLoad()
10602 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
10653 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); in CombineExtLoad()
10661 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
10669 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in CombineZExtLogicopShiftLoad()
10670 N0.getOpcode() == ISD::XOR) || in CombineZExtLogicopShiftLoad()
10671 N0.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
10672 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
10677 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
10678 N1.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
10679 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
10694 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) in CombineZExtLogicopShiftLoad()
10711 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, in CombineZExtLogicopShiftLoad()
10716 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, in CombineZExtLogicopShiftLoad()
10740 unsigned CastOpcode = Cast->getOpcode(); in matchVSelectOpSizesWithSetCC()
10754 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
10755 VSel.getOperand(0).getOpcode() != ISD::SETCC) in matchVSelectOpSizesWithSetCC()
10883 assert((N->getOpcode() == ISD::SIGN_EXTEND || in foldExtendedSignBitTest()
10884 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
10887 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || in foldExtendedSignBitTest()
10910 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
10919 if (N0.getOpcode() != ISD::SETCC) in foldSextSetcc()
10990 if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) in foldSextSetcc()
11049 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
11052 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
11125 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitSIGN_EXTEND()
11126 N0.getOpcode() == ISD::XOR) && in visitSIGN_EXTEND()
11128 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
11129 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitSIGN_EXTEND()
11143 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND()
11183 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSIGN_EXTEND()
11185 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
11192 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSIGN_EXTEND()
11194 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
11235 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
11241 if (N.getOpcode() != ISD::SETCC || in isTruncateOf()
11266 assert((Extend->getOpcode() == ISD::ZERO_EXTEND || in widenCtPop()
11267 Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op"); in widenCtPop()
11270 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) in widenCtPop()
11294 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
11316 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
11360 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
11361 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
11362 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
11394 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitZERO_EXTEND()
11395 N0.getOpcode() == ISD::XOR) && in visitZERO_EXTEND()
11397 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
11398 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitZERO_EXTEND()
11406 if (N0.getOpcode() == ISD::AND) { in visitZERO_EXTEND()
11424 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
11461 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
11506 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
11508 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitZERO_EXTEND()
11511 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
11527 return DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
11554 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
11555 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
11556 N0.getOpcode() == ISD::SIGN_EXTEND) in visitANY_EXTEND()
11557 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitANY_EXTEND()
11561 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
11574 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
11579 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
11580 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
11581 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
11633 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && in visitANY_EXTEND()
11649 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
11700 unsigned Opcode = N->getOpcode(); in visitAssertExt()
11706 if (N0.getOpcode() == Opcode && in visitAssertExt()
11710 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
11711 N0.getOperand(0).getOpcode() == Opcode) { in visitAssertExt()
11734 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
11735 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
11769 switch (N0.getOpcode()) { in visitAssertAlign()
11784 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); in visitAssertAlign()
11800 unsigned Opc = N->getOpcode(); in ReduceLoadWidth()
11859 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in ReduceLoadWidth()
11891 if (Mask->getOpcode() == ISD::AND && in ReduceLoadWidth()
11909 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in ReduceLoadWidth()
12022 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
12031 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
12043 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
12044 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
12045 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in visitSIGN_EXTEND_INREG()
12050 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in visitSIGN_EXTEND_INREG()
12063 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
12087 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
12172 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
12209 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
12220 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
12221 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
12222 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
12225 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitTRUNCATE()
12235 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) in visitTRUNCATE()
12248 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
12274 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { in visitTRUNCATE()
12286 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in visitTRUNCATE()
12309 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && in visitTRUNCATE()
12328 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
12329 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
12367 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
12388 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
12433 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { in visitTRUNCATE()
12454 if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) && in visitTRUNCATE()
12457 ((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) || in visitTRUNCATE()
12458 TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitTRUNCATE()
12463 return DAG.getNode(N0.getOpcode(), SL, VTs, X, Y, N0.getOperand(2)); in visitTRUNCATE()
12470 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
12472 if (N00.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
12473 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
12474 N00.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
12489 switch (N0.getOpcode()) { in visitTRUNCATE()
12502 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { in visitTRUNCATE()
12506 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); in visitTRUNCATE()
12515 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitTRUNCATE()
12518 hasOperation(N0.getOpcode(), VT)) { in visitTRUNCATE()
12530 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
12538 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
12592 switch (N0.getOpcode()) { in foldBitcastedFPLogic()
12616 LogicOp0.getOpcode() == ISD::BITCAST && in foldBitcastedFPLogic()
12620 if (N0.getOpcode() == ISD::OR) in foldBitcastedFPLogic()
12645 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && in visitBITCAST()
12667 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
12711 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
12712 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
12724 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
12728 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
12743 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
12746 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
12762 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && in visitBITCAST()
12826 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
12835 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
12843 if (Op.getOpcode() == ISD::BITCAST && in visitBITCAST()
13044 if (N.getOpcode() != ISD::FMUL) in visitFADDForFMACombine()
13072 if (CanReassociate && N0.getOpcode() == PreferredFusedOpcode && in visitFADDForFMACombine()
13073 N0.getOperand(2).getOpcode() == ISD::FMUL && N0.hasOneUse() && in visitFADDForFMACombine()
13077 } else if (CanReassociate && N1.getOpcode() == PreferredFusedOpcode && in visitFADDForFMACombine()
13078 N1.getOperand(2).getOpcode() == ISD::FMUL && N1.hasOneUse() && in visitFADDForFMACombine()
13095 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
13109 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
13133 if (N0.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
13135 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
13161 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
13163 if (N00.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
13177 if (N1.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
13179 if (N12.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
13196 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
13198 if (N10.getOpcode() == PreferredFusedOpcode) { in visitFADDForFMACombine()
13253 if (N.getOpcode() != ISD::FMUL) in visitFSUBForFMACombine()
13298 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
13311 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
13326 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
13345 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
13347 if (N00.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
13368 if (N0.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
13370 if (N00.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
13399 if (CanFuse && N0.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
13412 if (CanFuse && N1.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
13426 if (N0.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
13429 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
13451 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
13453 if (N00.getOpcode() == PreferredFusedOpcode) { in visitFSUBForFMACombine()
13473 if (N1.getOpcode() == PreferredFusedOpcode && in visitFSUBForFMACombine()
13474 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND && in visitFSUBForFMACombine()
13498 if (N1.getOpcode() == ISD::FP_EXTEND && in visitFSUBForFMACombine()
13499 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) { in visitFSUBForFMACombine()
13534 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
13565 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
13588 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
13630 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFADD()
13668 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
13694 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
13698 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
13709 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
13719 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
13731 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
13740 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
13752 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && in visitFADD()
13761 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
13771 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
13782 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
13838 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFSUB()
13888 N1.getOpcode() == ISD::FADD) { in visitFSUB()
13922 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFMUL()
13947 N0.getOpcode() == ISD::FMUL) { in visitFMUL()
13961 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && in visitFMUL()
13995 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && in visitFMUL()
13998 if (Select.getOpcode() != ISD::SELECT) in visitFMUL()
14006 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && in visitFMUL()
14102 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) && in visitFMA()
14110 if (N0.getOpcode() == ISD::FMUL && in visitFMA()
14132 if (N0.getOpcode() == ISD::FNEG && in visitFMA()
14150 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { in visitFMA()
14206 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { in combineRepeatedFPDivisors()
14208 if (U->getOperand(1).getOpcode() == ISD::FSQRT && in combineRepeatedFPDivisors()
14257 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFDIV()
14297 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
14300 } else if (N1.getOpcode() == ISD::FP_EXTEND && in visitFDIV()
14301 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
14308 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
14309 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
14316 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
14320 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
14323 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
14333 if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) in visitFDIV()
14370 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) in visitFDIV()
14399 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFREM()
14438 if ((N1.getOpcode() == ISD::FP_EXTEND || in CanCombineFCOPYSIGN_EXTEND_ROUND()
14439 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
14490 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
14491 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
14495 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
14499 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
14611 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
14615 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && in foldFPToIntToFP()
14649 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
14659 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
14660 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && in visitSINT_TO_FP()
14700 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
14718 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
14723 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
14724 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; in FoldIntToFPToInt()
14796 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
14800 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
14827 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { in visitFP_ROUND()
14847 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
14855 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
14861 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
14916 switch (N0.getOpcode()) { in visitFTRUNC()
14957 if (N0.getOpcode() == ISD::FSUB && in visitFNEG()
14978 unsigned Opc = N->getOpcode(); in visitFMinMax()
14992 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitFMinMax()
15051 if (N0.getOpcode() == ISD::FABS) in visitFABS()
15056 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
15072 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { in visitBRCOND()
15085 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
15106 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
15107 (N.getOpcode() == ISD::TRUNCATE && in rebuildSetCC()
15109 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
15111 if (N.getOpcode() == ISD::TRUNCATE) in rebuildSetCC()
15134 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { in rebuildSetCC()
15137 if (AndOp1.getOpcode() == ISD::Constant) { in rebuildSetCC()
15153 if (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
15160 while (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
15173 if (N.getOpcode() != ISD::XOR) in rebuildSetCC()
15179 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
15182 if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && in rebuildSetCC()
15221 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
15291 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
15364 if (Use.getUser()->getOpcode() != ISD::ADD && in CombineToPreIndexedLoadStore()
15365 Use.getUser()->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
15461 int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; in CombineToPreIndexedLoadStore()
15462 int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; in CombineToPreIndexedLoadStore()
15500 (PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) in shouldCombineToPostInc()
15534 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { in shouldCombineToPostInc()
15642 assert((Inc.getOpcode() != ISD::TargetConstant || in SplitIndexingFromLoad()
15645 if (Inc.getOpcode() == ISD::TargetConstant) { in SplitIndexingFromLoad()
16225 if (Use->getOpcode() != ISD::BITCAST) in canMergeExpensiveCrossRegisterBankCopy()
16442 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
16450 if (User->getOpcode() != ISD::TRUNCATE) in SliceUpLoad()
16493 if (SliceInst.getOpcode() != ISD::LOAD) in SliceUpLoad()
16495 assert(SliceInst->getOpcode() == ISD::LOAD && in SliceUpLoad()
16515 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
16564 else if (Chain->getOpcode() == ISD::TokenFactor && in CheckForMaskedLoad()
16655 unsigned Opc = Value.getOpcode(); in ReduceLoadOpStoreWidth()
16682 Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
16850 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. in isMulAddWithConstProfitable()
16886 if (OtherOp->getOpcode() == ISD::ADD && in isMulAddWithConstProfitable()
16985 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
16986 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
17159 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
17160 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
17254 if (N->getOpcode() == ISD::TokenFactor) { in checkMergeStoreCandidatesForDependencies()
17923 if (Value.getOpcode() == ISD::TargetConstantFP) in replaceStoreOfFPConstant()
18008 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
18090 if (N->getOpcode() != ISD::DELETED_NODE) in visitSTORE()
18148 if ((Value.getOpcode() == ISD::FP_ROUND || in visitSTORE()
18149 Value.getOpcode() == ISD::TRUNCATE) && in visitSTORE()
18169 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N)) in visitSTORE()
18208 switch (Chain.getOpcode()) { in visitLIFETIME_END()
18288 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) in splitMergedValStore()
18295 if (Op1.getOpcode() != ISD::SHL) { in splitMergedValStore()
18297 if (Op1.getOpcode() != ISD::SHL) in splitMergedValStore()
18313 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
18316 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
18323 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
18326 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
18356 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in combineInsertEltToShuffle()
18365 if (Vec.getOpcode() == ISD::VECTOR_SHUFFLE && Vec.hasOneUse() && in combineInsertEltToShuffle()
18366 InsertVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineInsertEltToShuffle()
18398 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in combineInsertEltToShuffle()
18434 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || in combineInsertEltToShuffle()
18501 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
18536 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
18559 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
18675 if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || in scalarizeExtractedBinop()
18696 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
18715 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
18722 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
18745 if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || in visitEXTRACT_VECTOR_ELT()
18746 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
18749 assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || in visitEXTRACT_VECTOR_ELT()
18753 VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; in visitEXTRACT_VECTOR_ELT()
18777 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && in visitEXTRACT_VECTOR_ELT()
18789 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
18819 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
18837 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_VECTOR_ELT()
18862 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
18875 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
18883 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
18898 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
18933 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
18960 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
18972 } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && in visitEXTRACT_VECTOR_ELT()
19038 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
19039 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
19094 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
19095 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
19133 assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecTruncToBitCast()
19152 if (Op.getOpcode() == ISD::BITCAST) in reduceBuildVecTruncToBitCast()
19164 if (In.getOpcode() != ISD::TRUNCATE) in reduceBuildVecTruncToBitCast()
19169 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
19326 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecToShuffleWithZero()
19353 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
19354 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffleWithZero()
19459 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
19662 unsigned Opc = Op.getOpcode(); in convertBuildVecZextToZext()
19665 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && in convertBuildVecZextToZext()
19737 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
19804 if (ISD::BITCAST == Op.getOpcode() && in combineConcatVectorOfScalars()
19807 else if (ISD::UNDEF == Op.getOpcode()) in combineConcatVectorOfScalars()
19873 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
19925 unsigned CastOpcode = N->getOperand(0).getOpcode(); in combineConcatVectorOfCasts()
19950 if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || in combineConcatVectorOfCasts()
20005 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) { in visitCONCAT_VECTORS()
20016 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
20028 if (Scalar->getOpcode() == ISD::TRUNCATE && in visitCONCAT_VECTORS()
20060 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); in visitCONCAT_VECTORS()
20072 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
20084 if (ISD::UNDEF == Op.getOpcode()) in visitCONCAT_VECTORS()
20087 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
20133 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
20165 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
20170 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
20184 unsigned BinOpcode = BinOp.getOpcode(); in narrowInsertExtractVectorBinOp()
20233 unsigned BOpcode = BinOp.getOpcode(); in narrowExtractedVectorBinOp()
20314 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) in narrowExtractedVectorBinOp()
20418 if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { in visitEXTRACT_SUBVECTOR()
20429 if (V.getOpcode() == ISD::BITCAST && in visitEXTRACT_SUBVECTOR()
20480 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
20518 if (V.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_SUBVECTOR()
20550 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
20592 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
20593 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
20757 if (S.getOpcode() == ISD::BUILD_VECTOR) { in combineShuffleOfScalars()
20759 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
20865 unsigned Opcode = N0.getOpcode(); in combineTruncationShuffle()
21071 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
21182 TLI.isBinOp(N0.getOpcode()) && N0.getNode()->getNumValues() == 1) { in visitVECTOR_SHUFFLE()
21191 SDValue NewBO = DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, in visitVECTOR_SHUFFLE()
21202 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
21209 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
21263 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
21266 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
21275 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && in visitVECTOR_SHUFFLE()
21305 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitVECTOR_SHUFFLE()
21310 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
21479 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21480 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
21497 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21498 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21512 if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21539 unsigned SrcOpcode = N0.getOpcode(); in visitVECTOR_SHUFFLE()
21542 (SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { in visitVECTOR_SHUFFLE()
21553 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21554 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21555 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21556 Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { in visitVECTOR_SHUFFLE()
21625 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitSCALAR_TO_VECTOR()
21684 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21692 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && in visitINSERT_SUBVECTOR()
21693 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21706 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
21723 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21732 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21740 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && in visitINSERT_SUBVECTOR()
21741 N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
21778 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
21793 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
21814 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
21824 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { in visitFP16_TO_FP()
21838 unsigned Opcode = N->getOpcode(); in visitVECREDUCE()
21870 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); in XformToShuffleWithZero()
21882 if (RHS.getOpcode() != ISD::BUILD_VECTOR) in XformToShuffleWithZero()
21959 unsigned Opcode = N->getOpcode(); in scalarizeBinOpOfSplats()
21985 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && in scalarizeBinOpOfSplats()
22009 unsigned Opcode = N->getOpcode(); in SimplifyVBinOp()
22047 Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
22057 Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
22071 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && in SimplifyVBinOp()
22072 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && in SimplifyVBinOp()
22093 return Concat.getOpcode() == ISD::CONCAT_VECTORS && in SimplifyVBinOp()
22131 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); in SimplifySelect()
22142 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
22170 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
22177 if (TheSelect->getOpcode() == ISD::SELECT_CC) { in SimplifySelectOps()
22184 if (Cmp.getOpcode() == ISD::SETCC) { in SimplifySelectOps()
22204 if (LHS.getOpcode() != RHS.getOpcode() || in SimplifySelectOps()
22212 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
22241 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
22242 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
22243 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), in SimplifySelectOps()
22270 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
22433 unsigned BinOpc = N1.getOpcode(); in foldSelectOfBinops()
22434 if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc)) in foldSelectOfBinops()
22473 bool IsFabs = N->getOpcode() == ISD::FABS; in foldSignChangeInBitcast()
22476 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) in foldSignChangeInBitcast()
22604 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
22697 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
22698 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in SimplifySelectCC()
22704 if ((Count.getOpcode() == ISD::CTLZ || in SimplifySelectCC()
22705 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && in SimplifySelectCC()
23149 switch (C.getOpcode()) { in GatherAllAliases()
23212 if (Chain.getOpcode() == ISD::TokenFactor) { in GatherAllAliases()