Lines Matching refs:OperIdx

233 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {  in addPhysRegDataDeps()  argument
234 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
243 bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() && in addPhysRegDataDeps()
272 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
274 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep); in addPhysRegDataDeps()
280 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep); in addPhysRegDataDeps()
291 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
293 MachineOperand &MO = MI->getOperand(OperIdx); in addPhysRegDeps()
321 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
322 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep); in addPhysRegDeps()
333 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg)); in addPhysRegDeps()
337 addPhysRegDataDeps(SU, OperIdx); in addPhysRegDeps()
364 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg)); in addPhysRegDeps()
395 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { in addVRegDefDeps() argument
397 MachineOperand &MO = MI->getOperand(OperIdx); in addVRegDefDeps()
414 for (int I = OperIdx + 1, E = MI->getNumOperands(); I != E; ++I) { in addVRegDefDeps()
447 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use, in addVRegDefDeps()
449 ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep); in addVRegDefDeps()
491 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
515 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { in addVRegUseDeps() argument
519 const MachineOperand &MO = MI->getOperand(OperIdx); in addVRegUseDeps()
525 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU)); in addVRegUseDeps()