Lines Matching refs:DefSU
312 SUnit *DefSU = I->SU; in addPhysRegDeps() local
313 if (DefSU == &ExitSU) in addPhysRegDeps()
315 if (DefSU != SU && in addPhysRegDeps()
317 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
321 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
322 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep); in addPhysRegDeps()
323 DefSU->addPred(Dep); in addPhysRegDeps()
481 SUnit *DefSU = V2SU.SU; in addVRegDefDeps() local
487 if (DefSU == SU) in addVRegDefDeps()
491 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
492 DefSU->addPred(Dep); in addVRegDefDeps()
502 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU)); in addVRegDefDeps()