244     unsigned Cascade = 0;  member
952   unsigned Cascade = ExtraRegInfo[VirtReg.reg()].Cascade;  in canEvictInterference()  local
953   if (!Cascade)  in canEvictInterference()
954     Cascade = NextCascade;  in canEvictInterference()
990       unsigned IntfCascade = ExtraRegInfo[Intf->reg()].Cascade;  in canEvictInterference()
991       if (Cascade <= IntfCascade) {  in canEvictInterference()
1117   unsigned Cascade = ExtraRegInfo[VirtReg.reg()].Cascade;  in evictInterference()  local
1118   if (!Cascade)  in evictInterference()
1119     Cascade = ExtraRegInfo[VirtReg.reg()].Cascade = NextCascade++;  in evictInterference()
1122                     << " interference: Cascade " << Cascade << '\n');  in evictInterference()
1146     assert((ExtraRegInfo[Intf->reg()].Cascade < Cascade ||  in evictInterference()
1149     ExtraRegInfo[Intf->reg()].Cascade = Cascade;  in evictInterference()
3088                     << ExtraRegInfo[VirtReg.reg()].Cascade << '\n');  in selectOrSplitImpl()