Lines Matching refs:buildZExt
975 MIRBuilder.buildZExt(DstReg, TmpReg); in narrowScalar()
1444 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); in widenScalarMergeValues()
1452 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalarMergeValues()
1894 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) in widenScalarAddSubShlSat()
2055 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalar()
2793 auto ZextVal = B.buildZExt(TargetTy, InsertReg); in buildBitFieldInsert()
3292 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); in lower()
3321 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); in lower()
5102 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); in multiplyRegisters()
5107 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); in multiplyRegisters()
6212 R = MIRBuilder.buildZExt(DstTy, R); in lowerFPTOSI()
6279 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); in lowerFPTRUNC_F64_TO_F16()
6308 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); in lowerFPTRUNC_F64_TO_F16()
6319 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); in lowerFPTRUNC_F64_TO_F16()
6323 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); in lowerFPTRUNC_F64_TO_F16()
6433 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); in lowerFCopySign()
6567 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues()
6573 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); in lowerMergeValues()
6853 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); in lowerInsert()