Lines Matching refs:buildUndef
284 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
329 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
846 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()
857 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()
1392 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); in moreElementsVectorSrc()
1402 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); in moreElementsVectorSrc()
1515 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()
1560 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); in widenWithUnmerge()
3498 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); in fewerElementsVectorImplicitDef()
4014 MIRBuilder.buildUndef(DstReg); in fewerElementsVectorExtractInsertVectorElt()
4254 Register Undef = MIRBuilder.buildUndef(NarrowDstTy).getReg(0); in reduceOperationWidth()
4537 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); in fewerElementsVectorShuffle()
4556 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); in fewerElementsVectorShuffle()
4561 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) in fewerElementsVectorShuffle()
6712 Val = MIRBuilder.buildUndef(DstTy).getReg(0); in lowerShuffleVector()
6727 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); in lowerShuffleVector()