Lines Matching refs:OpNum
88 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
169 unsigned OpNum = MI.getOperandNo(&MO); in isCrossCopy() local
170 DstSubIdx = MI.getOperand(OpNum+1).getImm(); in isCrossCopy()
229 unsigned OpNum = MI.getOperandNo(&MO); in transferUsedLanes() local
238 assert(OpNum % 2 == 1); in transferUsedLanes()
239 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes()
246 if (OpNum == 2) in transferUsedLanes()
258 assert(OpNum == 1); in transferUsedLanes()
262 assert(OpNum == 1); in transferUsedLanes()
292 unsigned OpNum = MI.getOperandNo(&Use); in transferDefinedLanesStep() local
295 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
308 unsigned OpNum, LaneBitmask DefinedLanes) const { in transferDefinedLanes() argument
313 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes()
320 if (OpNum == 2) { in transferDefinedLanes()
324 assert(OpNum == 1 && "INSERT_SUBREG must have two operands"); in transferDefinedLanes()
332 assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only"); in transferDefinedLanes()
401 unsigned OpNum = DefMI.getOperandNo(&MO); in determineInitialDefinedLanes() local
402 DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes); in determineInitialDefinedLanes()