Lines Matching refs:control
87 m_hbp_regs[bp_index].control = control_value; in SetHardwareBreakpoint()
94 m_hbp_regs[bp_index].control &= ~1; in SetHardwareBreakpoint()
124 uint32_t tempControl = m_hbp_regs[hw_idx].control; in ClearHardwareBreakpoint()
126 m_hbp_regs[hw_idx].control &= ~g_enable_bit; in ClearHardwareBreakpoint()
133 m_hbp_regs[hw_idx].control = tempControl; in ClearHardwareBreakpoint()
180 uint32_t tempControl = m_hbp_regs[i].control; in ClearAllHardwareBreakpoints()
183 m_hbp_regs[i].control &= ~g_enable_bit; in ClearAllHardwareBreakpoints()
190 m_hbp_regs[i].control = tempControl; in ClearAllHardwareBreakpoints()
202 if ((m_hbp_regs[bp_index].control & g_enable_bit) != 0) in BreakpointIsEnabled()
295 m_hwp_regs[wp_index].control = control_value; in SetHardwareWatchpoint()
302 m_hwp_regs[wp_index].control &= ~g_enable_bit; in SetHardwareWatchpoint()
332 uint32_t tempControl = m_hwp_regs[wp_index].control; in ClearHardwareWatchpoint()
335 m_hwp_regs[wp_index].control &= ~g_enable_bit; in ClearHardwareWatchpoint()
342 m_hwp_regs[wp_index].control = tempControl; in ClearHardwareWatchpoint()
364 uint32_t tempControl = m_hwp_regs[i].control; in ClearAllHardwareWatchpoints()
367 m_hwp_regs[i].control &= ~g_enable_bit; in ClearAllHardwareWatchpoints()
374 m_hwp_regs[i].control = tempControl; in ClearAllHardwareWatchpoints()
390 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { in GetWatchpointSize()
408 if ((m_hwp_regs[wp_index].control & g_enable_bit) != 0) in WatchpointIsEnabled()