43 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionMIPS, InstructionMIPS)  in LLDB_PLUGIN_DEFINE_ADV()  argument
62 EmulateInstructionMIPS::EmulateInstructionMIPS(  in EmulateInstructionMIPS()  function in EmulateInstructionMIPS
187 void EmulateInstructionMIPS::Initialize() {  in Initialize()
192 void EmulateInstructionMIPS::Terminate() {  in Terminate()
196 ConstString EmulateInstructionMIPS::GetPluginNameStatic() {  in GetPluginNameStatic()
201 lldb_private::ConstString EmulateInstructionMIPS::GetPluginName() {  in GetPluginName()
206 const char *EmulateInstructionMIPS::GetPluginDescriptionStatic() {  in GetPluginDescriptionStatic()
211 EmulateInstructionMIPS::CreateInstance(const ArchSpec &arch,  in CreateInstance()
213   if (EmulateInstructionMIPS::SupportsEmulatingInstructionsOfTypeStatic(  in CreateInstance()
217       return new EmulateInstructionMIPS(arch);  in CreateInstance()
224 bool EmulateInstructionMIPS::SetTargetTriple(const ArchSpec &arch) {  in SetTargetTriple()
229 const char *EmulateInstructionMIPS::GetRegisterName(unsigned reg_num,  in GetRegisterName()
598 bool EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,  in GetRegisterInfo()
680 EmulateInstructionMIPS::MipsOpcode *
681 EmulateInstructionMIPS::GetOpcodeForInstruction(const char *op_name) {  in GetOpcodeForInstruction()
682   static EmulateInstructionMIPS::MipsOpcode g_opcodes[] = {  in GetOpcodeForInstruction()
684       {"ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu,  in GetOpcodeForInstruction()
686       {"SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt, offset(rs)"},  in GetOpcodeForInstruction()
687       {"LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt, offset(base)"},  in GetOpcodeForInstruction()
688       {"SUBU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "SUBU rd, rs, rt"},  in GetOpcodeForInstruction()
689       {"ADDU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "ADDU rd, rs, rt"},  in GetOpcodeForInstruction()
690       {"LUI", &EmulateInstructionMIPS::Emulate_LUI, "LUI rt, immediate"},  in GetOpcodeForInstruction()
693       {"ADDIUSP_MM", &EmulateInstructionMIPS::Emulate_ADDIUSP,  in GetOpcodeForInstruction()
695       {"ADDIUS5_MM", &EmulateInstructionMIPS::Emulate_ADDIUS5,  in GetOpcodeForInstruction()
697       {"SWSP_MM", &EmulateInstructionMIPS::Emulate_SWSP, "SWSP rt,offset(sp)"},  in GetOpcodeForInstruction()
698       {"SWM16_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,  in GetOpcodeForInstruction()
700       {"SWM32_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,  in GetOpcodeForInstruction()
702       {"SWP_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,  in GetOpcodeForInstruction()
704       {"LWSP_MM", &EmulateInstructionMIPS::Emulate_LWSP, "LWSP rt,offset(sp)"},  in GetOpcodeForInstruction()
705       {"LWM16_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,  in GetOpcodeForInstruction()
707       {"LWM32_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,  in GetOpcodeForInstruction()
709       {"LWP_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,  in GetOpcodeForInstruction()
711       {"JRADDIUSP", &EmulateInstructionMIPS::Emulate_JRADDIUSP,  in GetOpcodeForInstruction()
722       {"LB", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
724       {"LBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
726       {"LBU", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
728       {"LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
730       {"LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
732       {"LD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
734       {"LDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
736       {"LDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
738       {"LLD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
740       {"LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
742       {"LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
744       {"LH", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
746       {"LHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
748       {"LHU", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
750       {"LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
752       {"LL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
754       {"LLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
756       {"LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
758       {"LW", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
760       {"LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
762       {"LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
764       {"LWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
766       {"LWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
768       {"LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
770       {"LWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
772       {"LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
774       {"LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
776       {"LLX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
778       {"LLXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
780       {"LLDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
783       {"SB", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
785       {"SBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
787       {"SC", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
789       {"SCE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
791       {"SCD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
793       {"SD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
795       {"SDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
797       {"SDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
799       {"SDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
801       {"SDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
803       {"SDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
805       {"SH", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
807       {"SHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
809       {"SUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
811       {"SWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
813       {"SWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
815       {"SWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
817       {"SWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
819       {"SWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
821       {"SWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
823       {"SWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
825       {"SWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
827       {"SCX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
829       {"SCXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
831       {"SCDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
835       {"LBU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
837       {"LHU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
839       {"LW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
841       {"LWGP_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
843       {"SH16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
845       {"SW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
847       {"SW_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
849       {"SB16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
853       {"BEQ", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQ rs,rt,offset"},  in GetOpcodeForInstruction()
854       {"BNE", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNE rs,rt,offset"},  in GetOpcodeForInstruction()
855       {"BEQL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQL rs,rt,offset"},  in GetOpcodeForInstruction()
856       {"BNEL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNEL rs,rt,offset"},  in GetOpcodeForInstruction()
857       {"BGEZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
859       {"BAL", &EmulateInstructionMIPS::Emulate_BAL, "BAL offset"},  in GetOpcodeForInstruction()
860       {"BGEZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
862       {"BALC", &EmulateInstructionMIPS::Emulate_BALC, "BALC offset"},  in GetOpcodeForInstruction()
863       {"BC", &EmulateInstructionMIPS::Emulate_BC, "BC offset"},  in GetOpcodeForInstruction()
864       {"BGEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZ rs,offset"},  in GetOpcodeForInstruction()
865       {"BLEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
867       {"BGEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
869       {"BLTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
871       {"BGTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
873       {"BEQZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
875       {"BNEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
877       {"BEQC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
879       {"BNEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
881       {"BLTC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
883       {"BGEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
885       {"BLTUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
887       {"BGEUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
889       {"BLTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLTZC rt,offset"},  in GetOpcodeForInstruction()
890       {"BLEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLEZC rt,offset"},  in GetOpcodeForInstruction()
891       {"BGEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGEZC rt,offset"},  in GetOpcodeForInstruction()
892       {"BGTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGTZC rt,offset"},  in GetOpcodeForInstruction()
893       {"BEQZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BEQZC rt,offset"},  in GetOpcodeForInstruction()
894       {"BNEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BNEZC rt,offset"},  in GetOpcodeForInstruction()
895       {"BGEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZL rt,offset"},  in GetOpcodeForInstruction()
896       {"BGTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZ rt,offset"},  in GetOpcodeForInstruction()
897       {"BGTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZL rt,offset"},  in GetOpcodeForInstruction()
898       {"BLEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZ rt,offset"},  in GetOpcodeForInstruction()
899       {"BLEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZL rt,offset"},  in GetOpcodeForInstruction()
900       {"BLTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZ rt,offset"},  in GetOpcodeForInstruction()
901       {"BLTZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
903       {"BLTZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
905       {"BLTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZL rt,offset"},  in GetOpcodeForInstruction()
906       {"BOVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
908       {"BNVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
910       {"J", &EmulateInstructionMIPS::Emulate_J, "J target"},  in GetOpcodeForInstruction()
911       {"JAL", &EmulateInstructionMIPS::Emulate_JAL, "JAL target"},  in GetOpcodeForInstruction()
912       {"JALX", &EmulateInstructionMIPS::Emulate_JAL, "JALX target"},  in GetOpcodeForInstruction()
913       {"JALR", &EmulateInstructionMIPS::Emulate_JALR, "JALR target"},  in GetOpcodeForInstruction()
914       {"JALR_HB", &EmulateInstructionMIPS::Emulate_JALR, "JALR.HB target"},  in GetOpcodeForInstruction()
915       {"JIALC", &EmulateInstructionMIPS::Emulate_JIALC, "JIALC rt,offset"},  in GetOpcodeForInstruction()
916       {"JIC", &EmulateInstructionMIPS::Emulate_JIC, "JIC rt,offset"},  in GetOpcodeForInstruction()
917       {"JR", &EmulateInstructionMIPS::Emulate_JR, "JR target"},  in GetOpcodeForInstruction()
918       {"JR_HB", &EmulateInstructionMIPS::Emulate_JR, "JR.HB target"},  in GetOpcodeForInstruction()
919       {"BC1F", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1F cc, offset"},  in GetOpcodeForInstruction()
920       {"BC1T", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1T cc, offset"},  in GetOpcodeForInstruction()
921       {"BC1FL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1FL cc, offset"},  in GetOpcodeForInstruction()
922       {"BC1TL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1TL cc, offset"},  in GetOpcodeForInstruction()
923       {"BC1EQZ", &EmulateInstructionMIPS::Emulate_BC1EQZ, "BC1EQZ ft, offset"},  in GetOpcodeForInstruction()
924       {"BC1NEZ", &EmulateInstructionMIPS::Emulate_BC1NEZ, "BC1NEZ ft, offset"},  in GetOpcodeForInstruction()
925       {"BC1ANY2F", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
927       {"BC1ANY2T", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
929       {"BC1ANY4F", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
931       {"BC1ANY4T", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
933       {"BNZ_B", &EmulateInstructionMIPS::Emulate_BNZB, "BNZ.b wt,s16"},  in GetOpcodeForInstruction()
934       {"BNZ_H", &EmulateInstructionMIPS::Emulate_BNZH, "BNZ.h wt,s16"},  in GetOpcodeForInstruction()
935       {"BNZ_W", &EmulateInstructionMIPS::Emulate_BNZW, "BNZ.w wt,s16"},  in GetOpcodeForInstruction()
936       {"BNZ_D", &EmulateInstructionMIPS::Emulate_BNZD, "BNZ.d wt,s16"},  in GetOpcodeForInstruction()
937       {"BZ_B", &EmulateInstructionMIPS::Emulate_BZB, "BZ.b wt,s16"},  in GetOpcodeForInstruction()
938       {"BZ_H", &EmulateInstructionMIPS::Emulate_BZH, "BZ.h wt,s16"},  in GetOpcodeForInstruction()
939       {"BZ_W", &EmulateInstructionMIPS::Emulate_BZW, "BZ.w wt,s16"},  in GetOpcodeForInstruction()
940       {"BZ_D", &EmulateInstructionMIPS::Emulate_BZD, "BZ.d wt,s16"},  in GetOpcodeForInstruction()
941       {"BNZ_V", &EmulateInstructionMIPS::Emulate_BNZV, "BNZ.V wt,s16"},  in GetOpcodeForInstruction()
942       {"BZ_V", &EmulateInstructionMIPS::Emulate_BZV, "BZ.V wt,s16"},  in GetOpcodeForInstruction()
945       {"B16_MM", &EmulateInstructionMIPS::Emulate_B16_MM, "B16 offset"},  in GetOpcodeForInstruction()
946       {"BEQZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
948       {"BNEZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
950       {"BEQZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
952       {"BNEZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
954       {"BGEZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
956       {"BLTZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
958       {"JALR16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALR16 rs"},  in GetOpcodeForInstruction()
959       {"JALRS16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALRS16 rs"},  in GetOpcodeForInstruction()
960       {"JR16_MM", &EmulateInstructionMIPS::Emulate_JR, "JR16 rs rs"},  in GetOpcodeForInstruction()
961       {"JRC16_MM", &EmulateInstructionMIPS::Emulate_JR, "JRC16 rs rs"},  in GetOpcodeForInstruction()
962       {"JALS_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALS target"},  in GetOpcodeForInstruction()
963       {"JALX_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALX target"},  in GetOpcodeForInstruction()
964       {"JALRS_MM", &EmulateInstructionMIPS::Emulate_JALRS, "JALRS rt, rs"},  in GetOpcodeForInstruction()
978 EmulateInstructionMIPS::GetSizeOfInstruction(lldb_private::DataExtractor &data,  in GetSizeOfInstruction()
998 bool EmulateInstructionMIPS::SetInstruction(const Opcode &insn_opcode,  in SetInstruction()
1045 bool EmulateInstructionMIPS::ReadInstruction() {  in ReadInstruction()
1062 bool EmulateInstructionMIPS::EvaluateInstruction(uint32_t evaluate_options) {  in EvaluateInstruction()
1137 bool EmulateInstructionMIPS::CreateFunctionEntryUnwind(  in CreateFunctionEntryUnwind()
1163 bool EmulateInstructionMIPS::nonvolatile_reg_p(uint32_t regnum) {  in nonvolatile_reg_p()
1184 bool EmulateInstructionMIPS::Emulate_ADDiu(llvm::MCInst &insn) {  in Emulate_ADDiu()
1236 bool EmulateInstructionMIPS::Emulate_SW(llvm::MCInst &insn) {  in Emulate_SW()
1300 bool EmulateInstructionMIPS::Emulate_LW(llvm::MCInst &insn) {  in Emulate_LW()
1347 bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) {  in Emulate_SUBU_ADDU()
1425 bool EmulateInstructionMIPS::Emulate_LUI(llvm::MCInst &insn) {  in Emulate_LUI()
1442 bool EmulateInstructionMIPS::Emulate_ADDIUSP(llvm::MCInst &insn) {  in Emulate_ADDIUSP()
1468 bool EmulateInstructionMIPS::Emulate_ADDIUS5(llvm::MCInst &insn) {  in Emulate_ADDIUS5()
1501 bool EmulateInstructionMIPS::Emulate_SWSP(llvm::MCInst &insn) {  in Emulate_SWSP()
1566 bool EmulateInstructionMIPS::Emulate_SWM16_32(llvm::MCInst &insn) {  in Emulate_SWM16_32()
1643 bool EmulateInstructionMIPS::Emulate_LWSP(llvm::MCInst &insn) {  in Emulate_LWSP()
1694 bool EmulateInstructionMIPS::Emulate_LWM16_32(llvm::MCInst &insn) {  in Emulate_LWM16_32()
1751 bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) {  in Emulate_JRADDIUSP()
1803 bool EmulateInstructionMIPS::Emulate_BXX_3ops(llvm::MCInst &insn) {  in Emulate_BXX_3ops()
1852 bool EmulateInstructionMIPS::Emulate_BXX_3ops_C(llvm::MCInst &insn) {  in Emulate_BXX_3ops_C()
1931 bool EmulateInstructionMIPS::Emulate_Bcond_Link_C(llvm::MCInst &insn) {  in Emulate_Bcond_Link_C()
2000 bool EmulateInstructionMIPS::Emulate_Bcond_Link(llvm::MCInst &insn) {  in Emulate_Bcond_Link()
2050 bool EmulateInstructionMIPS::Emulate_BXX_2ops(llvm::MCInst &insn) {  in Emulate_BXX_2ops()
2103 bool EmulateInstructionMIPS::Emulate_BXX_2ops_C(llvm::MCInst &insn) {  in Emulate_BXX_2ops_C()
2163 bool EmulateInstructionMIPS::Emulate_B16_MM(llvm::MCInst &insn) {  in Emulate_B16_MM()
2190 bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) {  in Emulate_Branch_MM()
2291 bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) {  in Emulate_JALRx16_MM()
2330 bool EmulateInstructionMIPS::Emulate_JALx(llvm::MCInst &insn) {  in Emulate_JALx()
2375 bool EmulateInstructionMIPS::Emulate_JALRS(llvm::MCInst &insn) {  in Emulate_JALRS()
2412 bool EmulateInstructionMIPS::Emulate_BAL(llvm::MCInst &insn) {  in Emulate_BAL()
2443 bool EmulateInstructionMIPS::Emulate_BALC(llvm::MCInst &insn) {  in Emulate_BALC()
2474 bool EmulateInstructionMIPS::Emulate_BC(llvm::MCInst &insn) {  in Emulate_BC()
2497 bool EmulateInstructionMIPS::Emulate_J(llvm::MCInst &insn) {  in Emulate_J()
2520 bool EmulateInstructionMIPS::Emulate_JAL(llvm::MCInst &insn) {  in Emulate_JAL()
2551 bool EmulateInstructionMIPS::Emulate_JALR(llvm::MCInst &insn) {  in Emulate_JALR()
2586 bool EmulateInstructionMIPS::Emulate_JIALC(llvm::MCInst &insn) {  in Emulate_JIALC()
2624 bool EmulateInstructionMIPS::Emulate_JIC(llvm::MCInst &insn) {  in Emulate_JIC()
2650 bool EmulateInstructionMIPS::Emulate_JR(llvm::MCInst &insn) {  in Emulate_JR()
2677 bool EmulateInstructionMIPS::Emulate_FP_branch(llvm::MCInst &insn) {  in Emulate_FP_branch()
2714 bool EmulateInstructionMIPS::Emulate_BC1EQZ(llvm::MCInst &insn) {  in Emulate_BC1EQZ()
2750 bool EmulateInstructionMIPS::Emulate_BC1NEZ(llvm::MCInst &insn) {  in Emulate_BC1NEZ()
2793 bool EmulateInstructionMIPS::Emulate_3D_branch(llvm::MCInst &insn) {  in Emulate_3D_branch()
2845 bool EmulateInstructionMIPS::Emulate_BNZB(llvm::MCInst &insn) {  in Emulate_BNZB()
2849 bool EmulateInstructionMIPS::Emulate_BNZH(llvm::MCInst &insn) {  in Emulate_BNZH()
2853 bool EmulateInstructionMIPS::Emulate_BNZW(llvm::MCInst &insn) {  in Emulate_BNZW()
2857 bool EmulateInstructionMIPS::Emulate_BNZD(llvm::MCInst &insn) {  in Emulate_BNZD()
2861 bool EmulateInstructionMIPS::Emulate_BZB(llvm::MCInst &insn) {  in Emulate_BZB()
2865 bool EmulateInstructionMIPS::Emulate_BZH(llvm::MCInst &insn) {  in Emulate_BZH()
2869 bool EmulateInstructionMIPS::Emulate_BZW(llvm::MCInst &insn) {  in Emulate_BZW()
2873 bool EmulateInstructionMIPS::Emulate_BZD(llvm::MCInst &insn) {  in Emulate_BZD()
2877 bool EmulateInstructionMIPS::Emulate_MSA_Branch_DF(llvm::MCInst &insn,  in Emulate_MSA_Branch_DF()
2937 bool EmulateInstructionMIPS::Emulate_BNZV(llvm::MCInst &insn) {  in Emulate_BNZV()
2941 bool EmulateInstructionMIPS::Emulate_BZV(llvm::MCInst &insn) {  in Emulate_BZV()
2945 bool EmulateInstructionMIPS::Emulate_MSA_Branch_V(llvm::MCInst &insn,  in Emulate_MSA_Branch_V()
2980 bool EmulateInstructionMIPS::Emulate_LDST_Imm(llvm::MCInst &insn) {  in Emulate_LDST_Imm()
3013 bool EmulateInstructionMIPS::Emulate_LDST_Reg(llvm::MCInst &insn) {  in Emulate_LDST_Reg()