Lines Matching refs:IVSigned

2621   const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation();  in EmitOMPOuterLoop()  local
2645 RT.emitForNext(*this, S.getBeginLoc(), IVSize, IVSigned, LoopArgs.IL, in EmitOMPOuterLoop()
2686 [&S, &LoopArgs, LoopExit, &CodeGenLoop, IVSize, IVSigned, &CodeGenOrdered, in EmitOMPOuterLoop()
2699 [IVSize, IVSigned, Loc, &CodeGenOrdered](CodeGenFunction &CGF) { in EmitOMPOuterLoop()
2700 CodeGenOrdered(CGF, Loc, IVSize, IVSigned); in EmitOMPOuterLoop()
2795 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPForOuterLoop() local
2805 IVSigned, Ordered, DipatchRTInputValues); in EmitOMPForOuterLoop()
2808 IVSize, IVSigned, Ordered, LoopArgs.IL, LoopArgs.LB, LoopArgs.UB, in EmitOMPForOuterLoop()
2816 const bool IVSigned) { in EmitOMPForOuterLoop() argument
2819 IVSigned); in EmitOMPForOuterLoop()
2835 const unsigned IVSize, const bool IVSigned) {} in emitEmptyOrdered() argument
2851 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeOuterLoop() local
2854 IVSize, IVSigned, /* Ordered = */ false, LoopArgs.IL, LoopArgs.LB, in EmitOMPDistributeOuterLoop()
3183 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPWorksharingLoop() local
3214 [IVSize, IVSigned, Ordered, IL, LB, UB, ST, StaticChunkedOne, Chunk, in EmitOMPWorksharingLoop()
3223 IVSize, IVSigned, Ordered, IL.getAddress(CGF), in EmitOMPWorksharingLoop()
5161 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeLoop() local
5178 IVSize, IVSigned, /* Ordered = */ false, IL.getAddress(*this), in EmitOMPDistributeLoop()