Lines Matching refs:OutputBecomesInput
11614 bool OutputBecomesInput = false; in getNDSWDS() local
11620 OutputBecomesInput = true; in getNDSWDS()
11639 OutputBecomesInput); in getNDSWDS()
11681 StringRef MangledName, bool OutputBecomesInput, in addAArch64VectorName() argument
11686 if (OutputBecomesInput) in addAArch64VectorName()
11697 bool OutputBecomesInput, in addAArch64AdvSIMDNDSNames() argument
11702 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11704 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11708 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11710 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11714 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11716 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11721 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11739 const bool OutputBecomesInput = std::get<2>(Data); in emitAArch64DeclareSimdFunction() local
11783 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11791 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11793 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11797 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11801 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11811 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11820 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11822 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11826 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11830 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()