165 	CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET);  in vx_attach()
182 		CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD  in vx_attach()
243 	CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);  in vx_init_locked()
245 	CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);  in vx_init_locked()
252 	CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |  in vx_init_locked()
254 	CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |  in vx_init_locked()
263 	CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff);  in vx_init_locked()
268 	CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE);  in vx_init_locked()
269 	CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);  in vx_init_locked()
289 	CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER |  in vx_setfilter()
398 	CSR_WRITE_2(sc, VX_COMMAND, STOP_TRANSCEIVER);  in vx_setlink()
401 	CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, 0);  in vx_setlink()
407 		CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, ENABLE_UTP);  in vx_setlink()
410 		CSR_WRITE_2(sc, VX_COMMAND, START_TRANSCEIVER);  in vx_setlink()
416 		CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, LINKBEAT_ENABLE);  in vx_setlink()
477 		CSR_WRITE_2(sc, VX_COMMAND,  in vx_start_locked()
486 	CSR_WRITE_2(sc, VX_COMMAND, SET_TX_AVAIL_THRESH | (8188 >> 2));  in vx_start_locked()
492 	CSR_WRITE_2(sc, VX_COMMAND, SET_TX_START_THRESH |  in vx_start_locked()
634 			CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);  in vx_txstat()
650 		CSR_WRITE_2(sc, VX_COMMAND, C_INTR_LATCH);  in vx_intr()
664 		CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | status);  in vx_intr()
805 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);  in vx_read()
890 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);  in vx_get()
1004 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISABLE);  in vx_stop()
1005 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);  in vx_stop()
1007 	CSR_WRITE_2(sc, VX_COMMAND, TX_DISABLE);  in vx_stop()
1008 	CSR_WRITE_2(sc, VX_COMMAND, STOP_TRANSCEIVER);  in vx_stop()
1010 	CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);  in vx_stop()
1012 	CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);  in vx_stop()
1014 	CSR_WRITE_2(sc, VX_COMMAND, C_INTR_LATCH);  in vx_stop()
1015 	CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK);  in vx_stop()
1016 	CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK);  in vx_stop()
1017 	CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER);  in vx_stop()