Lines Matching refs:temp
293 uint32_t temp; in xhci_reset_command_queue_locked() local
297 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
298 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
300 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
309 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); in xhci_reset_command_queue_locked()
312 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
319 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
320 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
358 uint32_t temp; in xhci_start_controller() local
378 temp = XREAD4(sc, oper, XHCI_USBSTS); in xhci_start_controller()
381 XWRITE4(sc, oper, XHCI_USBSTS, temp); in xhci_start_controller()
443 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_start_controller()
444 temp |= XHCI_IMAN_INTR_ENA; in xhci_start_controller()
445 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_start_controller()
466 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_start_controller()
467 if (!temp) in xhci_start_controller()
470 if (temp) { in xhci_start_controller()
490 uint32_t temp; in xhci_halt_controller() local
505 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_halt_controller()
506 if (temp) in xhci_halt_controller()
510 if (!temp) { in xhci_halt_controller()
520 uint32_t temp = 0; in xhci_reset_controller() local
530 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | in xhci_reset_controller()
532 if (!temp) in xhci_reset_controller()
536 if (temp) { in xhci_reset_controller()
547 uint32_t temp; in xhci_init() local
586 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); in xhci_init()
588 DPRINTF("HCS0 = 0x%08x\n", temp); in xhci_init()
591 if (XHCI_HCS0_CSZ(temp)) { in xhci_init()
598 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && in xhci_init()
607 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); in xhci_init()
610 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); in xhci_init()
619 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); in xhci_init()
626 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); in xhci_init()
628 DPRINTF("HCS2=0x%08x\n", temp); in xhci_init()
631 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); in xhci_init()
642 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); in xhci_init()
646 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); in xhci_init()
649 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + in xhci_init()
650 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; in xhci_init()
895 uint32_t temp; in xhci_check_transfer() local
906 temp = le32toh(trb->dwTrb2); in xhci_check_transfer()
908 remainder = XHCI_TRB_2_REM_GET(temp); in xhci_check_transfer()
909 status = XHCI_TRB_2_ERROR_GET(temp); in xhci_check_transfer()
911 temp = le32toh(trb->dwTrb3); in xhci_check_transfer()
912 epno = XHCI_TRB_3_EP_GET(temp); in xhci_check_transfer()
913 index = XHCI_TRB_3_SLOT_GET(temp); in xhci_check_transfer()
978 temp = le32toh(td->td_trb[i].dwTrb2); in xhci_check_transfer()
979 remainder += XHCI_TRB_2_BYTES_GET(temp); in xhci_check_transfer()
1074 uint32_t temp; in xhci_interrupt_poll() local
1096 temp = le32toh(phwr->hwr_events[i].dwTrb3); in xhci_interrupt_poll()
1098 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; in xhci_interrupt_poll()
1103 event = XHCI_TRB_3_TYPE_GET(temp); in xhci_interrupt_poll()
1163 uint32_t temp; in xhci_do_command() local
1195 temp = trb->dwTrb3; in xhci_do_command()
1198 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1200 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1202 temp &= ~htole32(XHCI_TRB_3_TC_BIT); in xhci_do_command()
1204 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1218 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1222 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1226 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1262 temp = le32toh(trb->dwTrb3); in xhci_do_command()
1269 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && in xhci_do_command()
1270 (temp & XHCI_TRB_3_BSR_BIT) == 0) { in xhci_do_command()
1284 temp = le32toh(sc->sc_cmd_result[0]); in xhci_do_command()
1285 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) in xhci_do_command()
1302 uint32_t temp;
1308 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1310 trb.dwTrb3 = htole32(temp);
1320 uint32_t temp; in xhci_cmd_enable_slot() local
1333 temp = le32toh(trb.dwTrb3); in xhci_cmd_enable_slot()
1335 *pslot = XHCI_TRB_3_SLOT_GET(temp); in xhci_cmd_enable_slot()
1345 uint32_t temp; in xhci_cmd_disable_slot() local
1351 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | in xhci_cmd_disable_slot()
1354 trb.dwTrb3 = htole32(temp); in xhci_cmd_disable_slot()
1364 uint32_t temp; in xhci_cmd_set_address() local
1370 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | in xhci_cmd_set_address()
1374 temp |= XHCI_TRB_3_BSR_BIT; in xhci_cmd_set_address()
1376 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_address()
1390 uint32_t temp; in xhci_set_address() local
1464 temp = le32toh(sc->sc_cmd_result[0]); in xhci_set_address()
1466 XHCI_TRB_2_ERROR_GET(temp) == in xhci_set_address()
1484 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); in xhci_set_address()
1485 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); in xhci_set_address()
1513 uint32_t temp; in xhci_cmd_configure_ep() local
1519 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | in xhci_cmd_configure_ep()
1523 temp |= XHCI_TRB_3_DCEP_BIT; in xhci_cmd_configure_ep()
1525 trb.dwTrb3 = htole32(temp); in xhci_cmd_configure_ep()
1535 uint32_t temp; in xhci_cmd_evaluate_ctx() local
1541 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | in xhci_cmd_evaluate_ctx()
1543 trb.dwTrb3 = htole32(temp); in xhci_cmd_evaluate_ctx()
1553 uint32_t temp; in xhci_cmd_reset_ep() local
1559 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | in xhci_cmd_reset_ep()
1564 temp |= XHCI_TRB_3_PRSV_BIT; in xhci_cmd_reset_ep()
1566 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_ep()
1576 uint32_t temp; in xhci_cmd_set_tr_dequeue_ptr() local
1582 temp = XHCI_TRB_2_STREAM_SET(stream_id); in xhci_cmd_set_tr_dequeue_ptr()
1583 trb.dwTrb2 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1585 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | in xhci_cmd_set_tr_dequeue_ptr()
1588 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1598 uint32_t temp; in xhci_cmd_stop_ep() local
1604 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | in xhci_cmd_stop_ep()
1609 temp |= XHCI_TRB_3_SUSP_EP_BIT; in xhci_cmd_stop_ep()
1611 trb.dwTrb3 = htole32(temp); in xhci_cmd_stop_ep()
1620 uint32_t temp; in xhci_cmd_reset_dev() local
1626 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | in xhci_cmd_reset_dev()
1629 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_dev()
1641 uint32_t temp; in xhci_interrupt() local
1653 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_interrupt()
1656 if (temp & XHCI_IMAN_INTR_PEND) in xhci_interrupt()
1657 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_interrupt()
1714 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) in xhci_setup_generic_chain_sub() argument
1732 shortpkt_old = temp->shortpkt; in xhci_setup_generic_chain_sub()
1733 len_old = temp->len; in xhci_setup_generic_chain_sub()
1739 td = temp->td; in xhci_setup_generic_chain_sub()
1740 td_next = td_first = temp->td_next; in xhci_setup_generic_chain_sub()
1744 if (temp->len == 0) { in xhci_setup_generic_chain_sub()
1746 if (temp->shortpkt) in xhci_setup_generic_chain_sub()
1751 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1756 average = temp->average; in xhci_setup_generic_chain_sub()
1758 if (temp->len < average) { in xhci_setup_generic_chain_sub()
1759 if (temp->len % temp->max_packet_size) { in xhci_setup_generic_chain_sub()
1760 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1762 average = temp->len; in xhci_setup_generic_chain_sub()
1780 temp->len -= average; in xhci_setup_generic_chain_sub()
1792 temp->len -= average; in xhci_setup_generic_chain_sub()
1798 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { in xhci_setup_generic_chain_sub()
1806 usbd_copy_out(temp->pc, temp->offset + buf_offset, in xhci_setup_generic_chain_sub()
1844 usbd_get_page(temp->pc, temp->offset + in xhci_setup_generic_chain_sub()
1860 temp->max_packet_size); in xhci_setup_generic_chain_sub()
1878 switch (temp->trb_type) { in xhci_setup_generic_chain_sub()
1881 XHCI_TRB_3_TBC_SET(temp->tbc) | in xhci_setup_generic_chain_sub()
1882 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); in xhci_setup_generic_chain_sub()
1885 } else if (temp->do_isoc_sync != 0) { in xhci_setup_generic_chain_sub()
1886 temp->do_isoc_sync = 0; in xhci_setup_generic_chain_sub()
1889 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); in xhci_setup_generic_chain_sub()
1895 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1901 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1911 temp->trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain_sub()
1916 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1922 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1985 if (temp->last_frame) { in xhci_setup_generic_chain_sub()
1993 temp->shortpkt = shortpkt_old; in xhci_setup_generic_chain_sub()
1994 temp->len = len_old; in xhci_setup_generic_chain_sub()
2002 if (temp->step_td != 0) { in xhci_setup_generic_chain_sub()
2016 temp->td = td; in xhci_setup_generic_chain_sub()
2017 temp->td_next = td_next; in xhci_setup_generic_chain_sub()
2023 struct xhci_std_temp temp; in xhci_setup_generic_chain() local
2029 temp.do_isoc_sync = 0; in xhci_setup_generic_chain()
2030 temp.step_td = 0; in xhci_setup_generic_chain()
2031 temp.tbc = 0; in xhci_setup_generic_chain()
2032 temp.tlbpc = 0; in xhci_setup_generic_chain()
2033 temp.average = xfer->max_hc_frame_size; in xhci_setup_generic_chain()
2034 temp.max_packet_size = xfer->max_packet_size; in xhci_setup_generic_chain()
2035 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); in xhci_setup_generic_chain()
2036 temp.pc = NULL; in xhci_setup_generic_chain()
2037 temp.last_frame = 0; in xhci_setup_generic_chain()
2038 temp.offset = 0; in xhci_setup_generic_chain()
2039 temp.multishort = xfer->flags_int.isochronous_xfr || in xhci_setup_generic_chain()
2049 temp.td = NULL; in xhci_setup_generic_chain()
2050 temp.td_next = td; in xhci_setup_generic_chain()
2073 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); in xhci_setup_generic_chain()
2080 temp.isoc_delta = 8; /* 1ms */ in xhci_setup_generic_chain()
2081 x += temp.isoc_delta - 1; in xhci_setup_generic_chain()
2082 x &= ~(temp.isoc_delta - 1); in xhci_setup_generic_chain()
2086 temp.isoc_delta = 1U << shift; in xhci_setup_generic_chain()
2087 x += temp.isoc_delta - 1; in xhci_setup_generic_chain()
2088 x &= ~(temp.isoc_delta - 1); in xhci_setup_generic_chain()
2108 temp.do_isoc_sync = 1; in xhci_setup_generic_chain()
2118 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + in xhci_setup_generic_chain()
2122 temp.isoc_frame = xfer->endpoint->isoc_next; in xhci_setup_generic_chain()
2123 temp.trb_type = XHCI_TRB_TYPE_ISOCH; in xhci_setup_generic_chain()
2133 temp.len = xfer->frlengths[0]; in xhci_setup_generic_chain()
2134 temp.pc = xfer->frbuffers + 0; in xhci_setup_generic_chain()
2135 temp.shortpkt = temp.len ? 1 : 0; in xhci_setup_generic_chain()
2136 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; in xhci_setup_generic_chain()
2137 temp.direction = 0; in xhci_setup_generic_chain()
2143 temp.last_frame = 1; in xhci_setup_generic_chain()
2146 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2150 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2151 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2152 temp.trb_type = xfer->flags_int.control_did_data ? in xhci_setup_generic_chain()
2157 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2158 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2159 temp.trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain()
2164 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2166 temp.direction = UE_GET_DIR(xfer->endpointno); in xhci_setup_generic_chain()
2173 temp.len = xfer->frlengths[x]; in xhci_setup_generic_chain()
2174 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && in xhci_setup_generic_chain()
2175 x != 0 && temp.multishort == 0); in xhci_setup_generic_chain()
2183 temp.last_frame = 1; in xhci_setup_generic_chain()
2185 temp.last_frame = 1; in xhci_setup_generic_chain()
2188 if (temp.len == 0) { in xhci_setup_generic_chain()
2192 temp.shortpkt = 0; in xhci_setup_generic_chain()
2194 temp.tbc = 0; in xhci_setup_generic_chain()
2195 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2206 temp.shortpkt = 1; in xhci_setup_generic_chain()
2210 if (temp.len > xfer->max_frame_size) in xhci_setup_generic_chain()
2211 temp.len = xfer->max_frame_size; in xhci_setup_generic_chain()
2214 tdpc = howmany(temp.len, xfer->max_packet_size); in xhci_setup_generic_chain()
2216 temp.tbc = howmany(tdpc, mult) - 1; in xhci_setup_generic_chain()
2217 temp.tlbpc = (tdpc % mult); in xhci_setup_generic_chain()
2219 if (temp.tlbpc == 0) in xhci_setup_generic_chain()
2220 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2222 temp.tlbpc--; in xhci_setup_generic_chain()
2227 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; in xhci_setup_generic_chain()
2230 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2233 temp.offset += xfer->frlengths[x - 1]; in xhci_setup_generic_chain()
2234 temp.isoc_frame += temp.isoc_delta; in xhci_setup_generic_chain()
2237 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2250 if (xhcictlstep || temp.sc->sc_ctlstep) { in xhci_setup_generic_chain()
2257 temp.step_td = (xfer->nframes != 0); in xhci_setup_generic_chain()
2259 temp.step_td = 0; in xhci_setup_generic_chain()
2261 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; in xhci_setup_generic_chain()
2262 temp.len = 0; in xhci_setup_generic_chain()
2263 temp.pc = NULL; in xhci_setup_generic_chain()
2264 temp.shortpkt = 0; in xhci_setup_generic_chain()
2265 temp.last_frame = 1; in xhci_setup_generic_chain()
2266 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; in xhci_setup_generic_chain()
2268 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2271 td = temp.td; in xhci_setup_generic_chain()
2303 uint32_t temp; in xhci_configure_mask() local
2344 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); in xhci_configure_mask()
2345 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); in xhci_configure_mask()
2346 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); in xhci_configure_mask()
2347 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); in xhci_configure_mask()
2364 uint32_t temp; in xhci_configure_endpoint() local
2401 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2408 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2429 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2432 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2438 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); in xhci_configure_endpoint()
2449 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); in xhci_configure_endpoint()
2451 temp = in xhci_configure_endpoint()
2463 temp |= XHCI_EPCTX_1_CERR_SET(3); in xhci_configure_endpoint()
2467 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2470 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); in xhci_configure_endpoint()
2473 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); in xhci_configure_endpoint()
2476 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); in xhci_configure_endpoint()
2482 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2484 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); in xhci_configure_endpoint()
2490 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | in xhci_configure_endpoint()
2495 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); in xhci_configure_endpoint()
2498 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); in xhci_configure_endpoint()
2502 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); in xhci_configure_endpoint()
2525 uint64_t temp; in xhci_configure_endpoint_by_xfer() local
2531 temp = pepext->physaddr + in xhci_configure_endpoint_by_xfer()
2537 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); in xhci_configure_endpoint_by_xfer()
2563 uint32_t temp; in xhci_configure_device() local
2611 temp = XHCI_SCTX_0_ROUTE_SET(route) | in xhci_configure_device()
2617 temp |= XHCI_SCTX_0_SPEED_SET(2); in xhci_configure_device()
2622 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2626 temp |= XHCI_SCTX_0_SPEED_SET(3); in xhci_configure_device()
2630 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2634 temp |= XHCI_SCTX_0_SPEED_SET(1); in xhci_configure_device()
2639 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2643 temp |= XHCI_SCTX_0_SPEED_SET(4); in xhci_configure_device()
2652 temp |= XHCI_SCTX_0_HUB_SET(1); in xhci_configure_device()
2654 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); in xhci_configure_device()
2656 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); in xhci_configure_device()
2659 temp |= XHCI_SCTX_1_NUM_PORTS_SET( in xhci_configure_device()
2669 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); in xhci_configure_device()
2680 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); in xhci_configure_device()
2682 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); in xhci_configure_device()
2685 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( in xhci_configure_device()
2696 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( in xhci_configure_device()
2698 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( in xhci_configure_device()
2706 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); in xhci_configure_device()
2712 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | in xhci_configure_device()
2715 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); in xhci_configure_device()
3340 sc->sc_hub_desc.temp[0] = sc->sc_conf; in xhci_roothub_exec()
3391 sc->sc_hub_desc.temp, in xhci_roothub_exec()
3392 sizeof(sc->sc_hub_desc.temp), in xhci_roothub_exec()
3403 sc->sc_hub_desc.temp[0] = 0; in xhci_roothub_exec()
3548 memset(sc->sc_hub_desc.temp, 0, 16); in xhci_roothub_exec()
4078 uint8_t temp; in xhci_device_init() local
4092 err = xhci_cmd_enable_slot(sc, &temp); in xhci_device_init()
4099 if (temp > sc->sc_noslot) { in xhci_device_init()
4104 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { in xhci_device_init()
4105 DPRINTF("slot %u already allocated.\n", temp); in xhci_device_init()
4112 udev->controller_slot_id = temp; in xhci_device_init()
4116 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); in xhci_device_init()
4120 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; in xhci_device_init()