166 #define	READ_REG(sc,r) \  macro
274 	sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) &  in safe_attach()
377 	devinfo = READ_REG(sc, SAFE_DEVINFO);  in safe_attach()
538 	stat = READ_REG(sc, SAFE_HM_STAT);  in safe_intr()
584 			READ_REG(sc, SAFE_PE_DMASTAT)));  in safe_intr()
1608 	w = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1610 		v = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1621 		v = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1632 		READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN);  in safe_rng_disable_short_cycle()
1639 		READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN);  in safe_rng_enable_short_cycle()
1648 	while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT)  in safe_rng_read()
1650 	return READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_read()
1676 	if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) {  in safe_rng()
1680 			READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm));  in safe_rng()
1685 			w = READ_REG(sc, SAFE_RNG_CNFG);  in safe_rng()
1695 			if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) {  in safe_rng()
1798 	v = READ_REG(sc, SAFE_PE_DMACFG) &~  in safe_reset_board()
1816 	v = READ_REG(sc, SAFE_PE_DMACFG);  in safe_init_board()
1841 			(READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff,  in safe_init_board()
2000 		, READ_REG(sc, SAFE_DMA_ENDIAN)  in safe_dump_dmastatus()
2001 		, READ_REG(sc, SAFE_DMA_SRCADDR)  in safe_dump_dmastatus()
2002 		, READ_REG(sc, SAFE_DMA_DSTADDR)  in safe_dump_dmastatus()
2003 		, READ_REG(sc, SAFE_DMA_STAT)  in safe_dump_dmastatus()
2012 		, READ_REG(sc, SAFE_HI_CFG)  in safe_dump_intrstate()
2013 		, READ_REG(sc, SAFE_HI_MASK)  in safe_dump_intrstate()
2014 		, READ_REG(sc, SAFE_HI_DESC_CNT)  in safe_dump_intrstate()
2015 		, READ_REG(sc, SAFE_HU_STAT)  in safe_dump_intrstate()
2016 		, READ_REG(sc, SAFE_HM_STAT)  in safe_dump_intrstate()
2023 	u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT);  in safe_dump_ringstate()